TMS320LF/LC240X DSP控制器：系统与外设详解

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"TMS320LF/LC240X DSP 控制器系统与外围设备参考指南" 本文档详细介绍了TMS320LF/LC240x系列数字信号处理器（DSP）控制器的系统架构及其外围接口的使用方法。TMS320LF/LC240x是德州仪器（TI）推出的一系列高性能、低功耗的嵌入式处理器，广泛应用于各种需要高效处理和控制的领域。 1. **系统结构**：这些控制器集成了丰富的片上资源，包括处理器内核、内存、以及多种外设接口。内核通常采用优化的C24x DSP指令集，能够快速执行复杂的数学运算。 2. **PLL（锁相环）**：PLL用于频率合成，可以将输入时钟频率倍增或分频，以满足不同外设工作频率的需求。用户可以通过软件配置来调整PLL参数，实现系统时钟的灵活管理。 3. **看门狗定时器**：这是一种硬件安全机制，如果主程序运行出现异常导致无法正常执行，看门狗定时器会触发复位，确保系统的稳定运行。 4. **I/O口**：控制器提供了多个可编程的输入/输出端口，用户可以根据需求配置为输入或输出，进行设备控制和数据交换。 5. **片外存储器接口**：支持外部RAM和ROM的连接，扩展系统存储空间，便于处理大量数据或存储程序代码。 6. **事件管理器（EVA/EVB）**：这些模块用于处理实时事件，如中断服务，可以连接传感器和其他设备，提供灵活的信号处理和控制功能。 7. **模数转换器（ADC）**：ADC用于将模拟信号转化为数字信号，是许多应用中的关键组件，如数据采集和信号处理系统。 8. **SCI（Serial Communication Interface）**：串行通信接口，常用于实现与其它设备的串行通信，如UART（通用异步收发传输器）。 9. **SPI（Serial Peripheral Interface）**：SPI是一种同步串行接口，用于连接和控制各种外围设备，如传感器、显示器等。 10. **CAN（Controller Area Network）**：控制器局域网络协议，是一种高效的车辆网络通信标准，适用于工业自动化和汽车电子等领域。 TI提供的参考指南详细阐述了每个外设的工作原理、配置步骤和使用示例，帮助开发者充分利用这些资源进行系统设计。同时，TI提醒用户在购买和使用产品时，注意查阅最新的技术文档，确保信息的准确性和完整性。尽管产品经过了质量控制测试，但TI不保证所有参数都经过具体测试，且产品销售条款中包含了关于保修、专利侵权和责任限制等内容。在某些半导体产品的应用中可能存在潜在风险，因此在设计和应用过程中应遵循最佳实践和安全标准。

Figures

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Contents

Figures

1–1 ’240x Device Overview 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 ’240x Device Architecture 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 System Control and Status Register 1 (SCSR1) — Address 07018h 2-3. . . . . . . . . . . . . . . . .

2–3 System Control and Status Register 2 (SCSR2) — Address 07019h 2-5. . . . . . . . . . . . . . . . .

2–4 Device Identification Number Register (DINR) — Address 701Ch 2-7. . . . . . . . . . . . . . . . . . .

2–5 Peripheral Interrupt Expansion Block Diagram 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Interrupt Requests 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 ’240x Interrupt Response and Flow 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Interrupt Flag Register (IFR) — Address 0006h 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Interrupt Mask Register (IMR) — Address 0004h 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Peripheral Interrupt Vector Register (PIVR)— Address 701Eh 2-27. . . . . . . . . . . . . . . . . . . . . .

2–11 Peripheral Interrupt Request Register 0 (PIRQR0) — Address 7010h 2-28. . . . . . . . . . . . . . .

2–12 Peripheral Interrupt Request Register 1 (PIRQR1) — Address 7011h 2-29. . . . . . . . . . . . . . .

2–13 Peripheral Interrupt Request Register 2 (PIRQR2) — Address 7012h 2-30. . . . . . . . . . . . . . .

2–14 Peripheral Interrupt Acknowledge Register 0 (PIACKR0) — Address 7014h 2-31. . . . . . . . .

2–15 Peripheral Interrupt Acknowledge Register 1 (PIACKR1) — Address 7015h 2-32. . . . . . . . .

2–16 Peripheral Interrupt Acknowledge Register 2 (PIACKR2) — Address 7016h 2-33. . . . . . . . .

2–17 External Interrupt 1 Control Register (XINT1CR) — Address 7070h 2-36. . . . . . . . . . . . . . . . .

2–18 External Interrupt 2 Control Register (XINT2CR) — Address 7071h 2-37. . . . . . . . . . . . . . . . .

3–1 Memory Map for ’LF2407 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Memory Map for ’LF2406 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Memory Map for ’LF2402 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Memory Map for ’LC2406 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Memory Map for ’LC2404 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Memory Map for ’LC2402 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Program Memory Map for ’LF2407 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 ’2407 Peripheral Memory Map 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Data Memory Pages 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 I/O Space Address Map for ’240x 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Program Address/Data — Visibility Functional Timing 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 Data Address/ Data — Visibility Functional Timing 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 ’240x Wait-State Generator Control Register (WSGR) —

I/O-Space Address FFFFh (’240x) 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Shared Pin Configuration 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 I/O Mux Control Register A (MCRA) — Address 7090h 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 I/O Mux Control Register B (MCRB) — Address 7092h 5-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

xviii

5–4 I/O Mux Control Register C (MCRC) — Address 7094h 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Port A Data and Direction Control Register (PADATDIR) 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Port B Data and Direction Control Register (PBDATDIR) 5-11. . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Port C Data and Direction Control Register (PCDATDIR) 5-12. . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Port D Data and Direction Control Register (PDDATDIR) 5-13. . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Port E Data and Direction Control Register (PEDATDIR) 5-14. . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Port F Data and Direction Control Register (PFDATDIR) 5-15. . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Event Manager (EVA) Block Diagram 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Event Manager (EVB) Block Diagram 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 General-Purpose Timer Block Diagram (x = 2 or 4)

[when x = 2: y = 1 and n = 2;

when x = 4: y = 3 and n = 4] 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 GP Timer Continuous Up-Counting Mode (TxPR = 3 or 2) 6-23. . . . . . . . . . . . . . . . . . . . . . . . .

6–5 GP Timer Directional Up-/Down-Counting Mode: Prescale Factor 1 and TxPR = 3 6-24. . . .

6–6 GP Timer Continuous Up-/Down-Counting Mode (TxPR = 3 or 2) 6-25. . . . . . . . . . . . . . . . . . .

6–7 GP Timer Compare/PWM Output in Up-Counting Mode 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . .

6–8 GP Timer Compare/PWM Output in Up-/Down-Counting Modes 6-28. . . . . . . . . . . . . . . . . . . .

6–9 Timer Control Register (TxCON; x = 1, 2, 3, or 4) — Addresses 7404h (T1),

7408h (T2), 7504h (T3), and 7508h (T4) 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 GP Timer Control Register A (GPTCONA) — Address 7400h 6-33. . . . . . . . . . . . . . . . . . . . . .

6–11 GP Timer Control Register B (GPTCONB) — Address 7500h 6-34. . . . . . . . . . . . . . . . . . . . . .

6–12 Compare Unit Block Diagram

(For EVA: x = 1, 2, 3; y = 1, 3, 5; z = 1.

For EVB: x = 4, 5, 6; y = 7, 9, 11; z = 2) 6-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–13 Compare Control Register A (COMCONA) — Address 7411h 6-39. . . . . . . . . . . . . . . . . . . . . .

6–14 Compare Control Register B (COMCONB) — Address 7511h 6-41. . . . . . . . . . . . . . . . . . . . . .

6–15 Compare Action Control Register A (ACTRA) — Address 7413h 6-42. . . . . . . . . . . . . . . . . . .

6–16 Compare Action Control Register B (ACTRB) — Address 7513h 6-44. . . . . . . . . . . . . . . . . . .

6–17 PWM Circuits Block Diagram 6-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–18 Dead-Band Timer Control Register A (DBTCONA) — Address xx15h 6-48. . . . . . . . . . . . . . .

6–19 Dead-Band Timer Control Register B (DBTCONB) — Address xx15h 6-49. . . . . . . . . . . . . . .

6–20 Dead-Band Unit Block Diagram (x = 1, 2, or 3) 6-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–21 Output Logic Block Diagram (x = 1, 2, or 3; y = 1, 2, 3, 4, 5, or 6) 6-54. . . . . . . . . . . . . . . . . . .

6–22 Asymmetric PWM Waveform Generation With Compare Unit and PWM Circuits

(x = 1, 3, or 5) 6-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–23 Symmetric PWM Waveform Generation With Compare Units and PWM

Circuits (x = 1, 3, or 5) 6-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–24 3-Phase Power Inverter Schematic Diagram 6-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–25 Basic Space Vectors and Switching Patterns 6-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–26 Symmetric Space Vector PWM Waveforms 6-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–27 Capture Units Block Diagram (EVA) 6-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–28 Capture Units Block Diagram (EVB) 6-68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–29 Capture Control Register A (CAPCONA) — Address 7420h 6-70. . . . . . . . . . . . . . . . . . . . . . .

6–30 Capture Control Register B (CAPCONB) — Address 7520h 6-72. . . . . . . . . . . . . . . . . . . . . . .

6–31 Capture FIFO Status Register A (CAPFIFOA) — Address 7422h 6-74. . . . . . . . . . . . . . . . . . .

6–32 Capture FIFO Status Register B (CAPFIFOB) — Address 7522h 6-75. . . . . . . . . . . . . . . . . . .

6–33 Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVA 6-78. . . . . . . . . . . . . . . . . . .

Figures

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Contents

6–34 Quadrature Encoder Pulse (QEP) Circuit Block Diagram for EVB 6-79. . . . . . . . . . . . . . . . . . .

6–35 Quadrature Encoded Pulses and Decoded Timer Clock and Direction 6-80. . . . . . . . . . . . . . .

6–36 EVA Interrupt Flag Register A (EVAIFRA) — Address 742Fh 6-85. . . . . . . . . . . . . . . . . . . . . . .

6–37 EVA Interrupt Flag Register B (EVAIFRB) — Address 7430h 6-87. . . . . . . . . . . . . . . . . . . . . . .

6–38 EVA Interrupt Flag Register C (EVAIFRC) — Address 7431h 6-88. . . . . . . . . . . . . . . . . . . . . .

6–39 EVA Interrupt Mask Register A (EVAIMRA) — Address 742Ch 6-89. . . . . . . . . . . . . . . . . . . . .

6–40 EVA Interrupt Mask Register B (EVAIMRB) — Address 742Dh 6-90. . . . . . . . . . . . . . . . . . . . .

6–41 EVA Interrupt Mask Register C (EVAIMRC) — Address 742Eh 6-90. . . . . . . . . . . . . . . . . . . . .

6–42 EVB Interrupt Flag Register A (EVBIFRA) — Address 752Fh 6-91. . . . . . . . . . . . . . . . . . . . . .

6–43 EVB Interrupt Flag Register B (EVBIFRB) — Address 7530h 6-93. . . . . . . . . . . . . . . . . . . . . .

6–44 EVB Interrupt Flag Register C (EVBIFRC) — Address 7531h 6-94. . . . . . . . . . . . . . . . . . . . . .

6–45 EVB Interrupt Mask Register A (EVBIMRA) — Address 752Ch 6-95. . . . . . . . . . . . . . . . . . . . .

6–46 EVB Interrupt Mask Register B (EVBIMRB) — Address 752Dh 6-96. . . . . . . . . . . . . . . . . . . . .

6–47 EVB Interrupt Mask Register C (EVBIMRC) — Address 752Eh 6-96. . . . . . . . . . . . . . . . . . . . .

7–1 Block Diagram of Autosequenced ADC in Cascaded Mode 7-5. . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Block Diagram of Autosequenced ADC With Dual Sequencers 7-6. . . . . . . . . . . . . . . . . . . . . .

7–3 Example of Event Manager Triggers to Start the Sequencer 7-10. . . . . . . . . . . . . . . . . . . . . . .

7–4 Interrupt Operation During Sequenced Conversions 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 ADC Conversion Time 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 Clock Prescalers in ’240x ADC 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 ADC Control Register 1 (ADCTRL1) — Address 70A0h 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 ADC Control Register 2 (ADCTRL2) — Address 70A1h 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Maximum Conversion Channels Register (MAX_CONV) — Address 70A2h 7-27. . . . . . . . .

7–10 Autosequence Status Register (AUTO_SEQ_SR) — Address 70A7h 7-29. . . . . . . . . . . . . . .

7–11 ADC Input Channel Select Sequencing Control Registers (CHSELSEQn) 7-31. . . . . . . . . . .

7–12 ADC Conversion Result Buffer Registers 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 SCI Block Diagram 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 Typical SCI Data Frame Formats 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 Idle-Line Multiprocessor Communication Format 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Double-Buffered WUT and TXSHF 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Address-Bit Multiprocessor Communication Format 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–6 SCI Asynchronous Communications Format 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 SCI RX Signals in Communication Modes 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–8 SCI TX Signals in Communications Modes 8-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–9 SCI Control Registers 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–10 SCI Communication Control Register (SCICCR) — Address 7050h 8-20. . . . . . . . . . . . . . . . .

8–11 SCI Control Register 1 (SCICTL1) — Address 7051h 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–12 Baud-Select MSbyte Register (SCIHBAUD) — Address 7052h 8-25. . . . . . . . . . . . . . . . . . . . .

8–13 Baud-Select LSbyte Register (SCILBAUD) — Address 7053h 8-25. . . . . . . . . . . . . . . . . . . . . .

8–14 SCI Control Register 2 (SCICTL2) — Address 7054h 8-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–15 Receiver Status Register (SCIRXST) — Address 7055h 8-27. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–16 Register SCIRXST Bit Associations — Address 7055h 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–17 Emulation Data Buffer Register (SCIRXEMU) — Address 7056h 8-30. . . . . . . . . . . . . . . . . . .

8–18 Receiver Data Buffer (SCIRXBUF) — Address 7057h 8-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

8–19 Transmit Data Buffer Register (SCITXBUF) — Address 7059h 8-30. . . . . . . . . . . . . . . . . . . . .

8–20 SCI Priority Control Register (SCIPRI) — Address 705Fh 8-31. . . . . . . . . . . . . . . . . . . . . . . . .

9–1 SPI Module Block Diagram 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–2 SPI Master/Slave Connection 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–3 SPICLK Signal Options 9-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–4 SPI: SPICLK-CLKOUT Characteristic when (BRR + 1) is Odd, BRR > 3, and

CLOCK POLARITY = 1 9-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–5 Five Bits per Character 9-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–6 SPI Control Registers 9-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–7 SPI Configuration Control Register (SPICCR) — Address 7040h 9-18. . . . . . . . . . . . . . . . . . .

9–8 SPI Operation Control Register (SPICTL) — Address 7041h 9-20. . . . . . . . . . . . . . . . . . . . . . .

9–9 SPI Status Register (SPISTS) — Address 7042h 9-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–10 SPI Baud Rate Register (SPIBRR) — Address 7044h 9-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–11 SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h 9-24. . . . . . . . . . . . . . . . . . . .

9–12 SPI Serial Receive Buffer Register (SPIRXBUF) — Address 7047h 9-25. . . . . . . . . . . . . . . . .

9–13 SPI Serial Transmit Buffer Register (SPITXBUF) — Address 7048h 9-26. . . . . . . . . . . . . . . .

9–14 SPI Serial Data Register (SPIDAT) — Address 7049h 9-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–15 SPI Priority Control Register (SPIPRI) — Address 704Fh 9-28. . . . . . . . . . . . . . . . . . . . . . . . . .

9–16 CLOCK_POLARITY = 0, CLOCK_PHASE = 0 (All data transitions are during

the rising edge. Inactive level is low.) 9-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–17 CLOCK_POLARITY = 0, CLOCK_PHASE = 1 (Add data transitions are during

the rising edge, but delayed by half clock cycle. Inactive level is low.) 9-30. . . . . . . . . . . . . . .

9–18 CLOCK_POLARITY = 1, CLOCK_PHASE = 0 (All data transitions are during

the falling edge. Inactive level is high.) 9-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–19 CLOCK_POLARITY = 1, CLOCK_PHASE = 1 (Add data transitions are during

the falling edge, but delayed by half clock cycle. Inactive level is high.) 9-32. . . . . . . . . . . . . .

9–20 SPISTE Behavior in Master Mode (Master lowers SPISTE during the entire 16 bits

of transmission.) 9-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–21 SPISTE Behavior in Slave Mode (Slave’s SPISTE is lowered during the entire 16 bits

of transmission.) 9-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–1 CAN Data Frame 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–2 TMS320x240x CAN Module Block Diagram 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–3 TMS320x240x CAN Module Memory Space 10-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–4 CAN Data Frame 10-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–5 Message Identifier for High Word Mailboxes 0–5 (MSGIDnH) 10-10. . . . . . . . . . . . . . . . . . . . .

10–6 Message Identifier for Low Word Mailboxes 0–5 (MSGIDnL) 10-11. . . . . . . . . . . . . . . . . . . . . .

10–7 Message Control Field (MSGCTRLn) 10-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–8 Remote Frame Requests 10-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–9 Local Acceptance Mask Register n (0, 1) High Word (LAMn_H) 10-17. . . . . . . . . . . . . . . . . . .

10–10 Local Acceptance Mask Register n (0, 1) Low Word (LAMn_L) 10-17. . . . . . . . . . . . . . . . . . . .

10–11 Mailbox Direction/Enable Register (MDER) — Address 7100h 10-18. . . . . . . . . . . . . . . . . . . .

10–12 Transmission Control Register (TCR) — Address 7101h 10-19. . . . . . . . . . . . . . . . . . . . . . . . .

10–13 Receive Control Register (RCR) — Address 7102h 10-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–14 Master Control Register (MCR) — Address 7103h 10-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–15 Bit Configuration Register 2 (BCR2) — Address 7104h 10-25. . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

xxi

Contents

10–16 Bit Configuration Register 1 (BCR1) — Address 7105h 10-25. . . . . . . . . . . . . . . . . . . . . . . . . . .

10–17 CAN Bit Timing 10-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–18 Global Status Register (GSR) — Address 7107h 10-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–19 Error Status Register (ESR) — Address 7106h 10-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–20 CAN Error Counter Register (CEC) — Address 7108h 10-31. . . . . . . . . . . . . . . . . . . . . . . . . . .

10–21 CAN Interrupt Flag Register (CAN_IFR) — Address 7109h 10-33. . . . . . . . . . . . . . . . . . . . . . .

10–22 CAN Interrupt Mask Register (CAN_IMR) — Address 710Ah 10-35. . . . . . . . . . . . . . . . . . . . . .

10–23 CAN Initialization 10-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–1 Block Diagram of the WD Module 11-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–2 WD Counter Register (WDCNTR) — Address 7023h 11-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–3 WD Reset Key Register (WDKEY) — Address 7025h 11-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–4 WD Timer Control Register (WDCR) — Address 7029h 11-9. . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1 ’LF2407 Memory Map for Program Space 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–2 ’LF2407 Memory Map for Data Space 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–3 Pump Control Register 13-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–4 Flash Control Register 13-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–5 Test Control Register 13-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–6 Sector Enable Register 13-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–7 ’240x Watchdog Clock Generation Logic 13-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–8 Functional Block Diagram for Boot_EN/XF Feature 13-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–9 Functional Block Diagram of XMIF Signals on ’LF2407 13-19. . . . . . . . . . . . . . . . . . . . . . . . . . .

B–1 Procedure for Generating Executable Files B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–1 Example Hardware Configuration for ’LF240x Boot ROM Operation C-4. . . . . . . . . . . . . . . . .

C–2 Memory Maps for the ’LF240x Devices in Microcontroller Mode C-5. . . . . . . . . . . . . . . . . . . . .

C–3 SPI Data Packet Definition C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–4 Flowchart for the Serial Loader Baud Rate Match Algorithm C-9. . . . . . . . . . . . . . . . . . . . . . . .

C–5 Flowcharts for (a) Serial Asynchronous Loader and the Fetch Header Routine C-10. . . . . . .

C–6 Flowchart for FETCH_SCI_WORD C-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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