On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
Kyrre Glette and Jim Torresen
University of Oslo
Department of Informatics
P.O. Box 1080 Blindern, 0316 Oslo, Norway
{kyrrehg,jimtoer}@ifi.uio.no
Moritoshi Yasunaga and Yoshiki Yamaguchi
University of Tsukuba
Graduate School of
Systems and Information Engineering
1-1-1 Ten-ou-dai, Tsukuba, Ibaraki, Japan
{yasunaga,yoshiki}@cs.tsukuba.ac.jp
Abstract
To increase the flexibility of single-chip evolvab le hard-
ware systems, we explore possibilities of systems with the
evolutionary algorithm implemented in software on an on-
chip processor. This gives higher flexibility compared to im-
plementing an evolutionary algorithm directly in hardware,
since the parameters and behaviour of the algorithm can
easily be changed, and complex operators are more feasible
to implement. In this paper a Xilinx MicroBlaze soft core
processor is used, and the system is implemented in a Xilinx
FPGA. A suitable hardware architecture for image recogni-
tion has been proposed, and it is applied to a face recogni-
tion task. Data buses and higher level functions have been
utilized in order to reduce the search space fo r the evolu-
tionary algorithm. Experiments have been performed on
the physical device, with software running in parallel with
fitness computation in digital logic. Results show that the
MicroBlaze system evolves at half the speed of a Pentium
M system running at 17 times the FPGA clock frequency.
The distinction of a certain face from others is performed
at 94.9% accuracy. In addition, the possibilities for evo-
lutionary adaptation over time are explored by introducing
changes in the training set. The system shows ability to
adapt to these changes.
1 Introduction
Evolvable h ardware (EHW) seems useful for systems
submitted to unpredictable, time-varying env ironments [20,
14]. Such systems will also often be p art of embedded ap-
plications, and therefore compact, on-chip solutions will be
preferred.
There have been undertaken some implementations of
single-chip evolution earlier. Kajitani et al have introduced
several LSI (Large-Scale Integrated Circuits) devices with
evolution performed in hardware [5, 6]. The benefit of such
an approach is the evolution speed but the problem is lack
of flexibility. This would be important since there are often
many degrees of freedom when evolving hardware systems.
Implementing complete evolution in an FPGA has been
proposed by Tufte and Haddow in [16]. The evolving de-
sign is here implemented in the same device as the evo-
lutionary algorithm. A similar approach is proposed by
Perkins et al in [9]. Significant speedup is achieved for non-
linear filtering compared to conventional processing. Sev-
eral custom accelerators in FPGA for solving a protein fold-
ing problem have been introduced by Shackleford et al [12].
On-chip evolution using a prototype of the VLSI (Very
Large-Scale Integration) POEtic chip has also been reported
[10]. A robot controller and logic functions were evolved.
The architecture, specialized for the implementation of bio-
inspired mechanisms, contains an on-chip custom proces-
sor, and a bio-inspired array of building blocks.
Running complete evolution of image filters within an
FGA has been reported by Martinek and Sekanina [7]. In
this work the evolution (mutatio n only) is implemented in
reconfigurable logic. Image filters were evolved in a few
seconds from corrupted and original pictures. This design
employs data buses, earlier proposed in [11] and [13], and
function-level building blocks, first proposed in [8].
The authors h ave earlier demonstrated System-On-Chip
evolution u sing an embedded hard processor core in an
FPGA [1]. This is accomplished b y integrating an evolu-
tionary algorithm running as software on a hard processor
IP core with the target EHW implemented in reconfigurable
logic. In this paper an alternative approach is explored by
using a soft processor core. This allows for portability to a
greater range of FPGAs, including cheaper devices.
In our system, all parts of the evolution (except the eval-
uation o f individuals which is implemented in digital logic)
are undertaken in software, providing a flexible system for
later modifications. This is slower than implementing the
evolution in dedicated hardware, but it is expected that the
fitness evaluation time will still be the most time consum-