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JEDEC Standard No. 79-4C

Page 8

2.9 DDP Single Rank (SR) x16 from two x8

The Single Rank (SR) x16 DDP (Dual Die Package) is comprised of two x8 devices connected in parallel. The intent is to place two

x8 devices in the physical footprint space of a x16. Unless noted otherwise, the functionality, operation, and timings of the SRx16

DDP are to be the same as the mono x8 device.

Figure 4 — Functional Block Diagram of SR x16 DDP

Figure 5 — Ballout of SR x16 DDP using MO-207

1 2 3 4 5 6 7 8 9

A VDDQ VSSQ DQU0 DQSU_c VSSQ VDDQ A

B VPP VSS VDD DQSU_t DQU1 VDD B

C VDDQ DQU4 DQU2 DQU3 DQU5 VSSQ C

D VDD VSSQ DQU6 DQU7 VSSQ VDDQ D

E VSS

DMU_n/

DBIU_n

VSSQ

DML_n

DBIL_n

VSSQ UZQ E

F VSSQ VDDQ DQSL_c DQL1 VDDQ LZQ F

G VDDQ DQL0 DQSL_t VDD VSS VDDQ G

H VSSQ DQL4 DQL2 DQL3 DQL5 VSSQ H

J VDD VDDQ DQL6 DQL7 VDDQ VDD J

K VSS CKE ODT CK_t CK_c VSS K

L VDD

WE_n/

A14

ACT_n CS_n

RAS_n/

A16

VDD L

M VREFCA BG0

A10/

A12/

BC_n

CAS_n/

A15

BG1 M

N VSS BA0 A4 A3 BA1 TEN N

P RESET_n A6 A0 A1 A5 ALERT_n P

R VDD A8 A2 A9 A7 VPP R

T VSS A11 PAR VSS A13 VDD T

Byte 1

(xx Meg x8 x16 banks)

Byte 0

(xx Meg x8 x16 banks)

BG[1:0]

BA[1:0]

A[13:0]

UDM_n/

UDBI_n

UZQ

CS_n

RAS_n/A16

CAS_n/A15

WE_n/A14

ACT_n

PAR

VrefCA

LDM_n/

LDBI_n

LZQ

CK_t

CK_c

CKE

ODT

TEN

RESET_n

ALERT_n

UDQ[7:0]

UDQS_t

UDQS_c

LDQ[7:0]

LDQS_t

LDQS_c

--`,``,``,``,,```````,``,-`-``,```,,,`---

JEDEC Standard No. 79-4C

Page 11

3.1 Simplified State Diagram (cont’d)

Table 11 — Simplified State Diagram Functions

3.2 Basic Functionality

The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen-banks, 4 bank group with 4

banks for each bank group for x4/x8 and eight-banks, 2 bank group with 4 banks for each bankgroup for x16 DRAM.

The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with

an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM

consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock

cycle data transfers at the I/O pins.

Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight

or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an ACTIVATE Command, which is

then followed by a Read or Write command. The address bits registered coincident with the ACTIVATE Command are used to select

the bank and row to be activated (BG0-BG1 in x4/8 and BG0 in x16 select the bankgroup; BA0-BA1 select the bank; A0-A17 select

the row; refer to “DDR4 SDRAM Addressing” on Section 2.8 for specific requirements). The address bits registered coincident with

the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge

command is to be issued (via A10), and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.

Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner.

The following sections provide detailed information covering device reset and initialization, register definition, command descriptions,

and device operation.

3.3 RESET and Initialization Procedure

For power-up and reset initialization, in order to prevent DRAM from functioning improperly default values for the following MR

settings need to be defined.

Gear down mode (MR3 A[3]) : 0 = 1/2 Rate

Per DRAM Addressability (MR3 A[4]) : 0 = Disable

Max Power Saving Mode (MR4 A[1]) : 0 = Disable

CS to Command/Address Latency (MR4 A[8:6]) : 000 = Disable

CA Parity Latency Mode (MR5 A[2:0]) : 000 = Disable

Hard Post Package Repair mode (MR4 A[13]) : 0 = Disable

Soft Post Package Repair mode (MR4 A[5]) : 0 = Disable

3.3.1 Power-up Initialization Sequence

The following sequence is required for POWER UP and Initialization and is shown in Figure 7.

1. Apply power (RESET_n and TEN are recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).

RESET_n needs to be maintained below 0.2 x VDD for minimum 200us with stable power and TEN needs to be maintained below

0.2 x VDD for minimum 700us with stable power. CKE is pulled “Low” anytime before RESET_n being de-asserted (min. time

10ns). The power voltage ramp time between 300mV to V

min must be no greater than 200ms; and during the ramp, V

≥

DDQ

and (V

-V

DDQ

) < 0.3volts. VPP must ramp at the same time or earlier than VDD and VPP must be equal to or higher than

VDD at all times.

• V

and V

DDQ

are driven from a single power converter output, AND

• The voltage levels on all pins other than V

DDQ

SSQ

must be less than or equal to V

DDQ

and V

on one side and

must be larger than or equal to V

SSQ

and V

on the other side. In addition, V

is limited to 0.76V max once power ramp is

finished, AND

• VrefCA tracks VDD/2.

• Apply V

without any slope reversal before or at the same time as V

DDQ

Abbreviation Function Abbreviation Function Abbreviation Function

ACT Activate Read RD,RDS4, RDS8 PDE Enter Power-down

PRE Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down

PREA PRECHARGE All Write WR, WRS4, WRS8 with/without CRC SRE Self-Refresh entry

MRS Mode Register Set Write A WRA,WRAS4, WRAS8 with/without CRC SRX Self-Refresh exit

REF

Refresh, Fine granularity

Refresh

RESET_n Start RESET procedure MPR Multi Purpose Register

TEN

Boundary Scan Mode

Enable

--`,``,``,``,,```````,``,-`-``,```,,,`---

JEDEC Standard No. 79-4C

Page 12

3.3.1 Power-up Initialization Sequence (cont’d)

• Apply V

DDQ

without any slope reversal before or at the same time as V

& VrefCA.

• Apply VPP without any slope reversal before or at the same time as VDD.

• The voltage levels on all pins other than V

DDQ

SSQ

must be less than or equal to V

DDQ

and V

on one side and

must be larger than or equal to V

SSQ

and V

on the other side.

2. After RESET_n is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start internal

initialization; this will be done independently of external clocks.

3. Clocks (CK_t,CK_c) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since

CKE is a synchronous signal, the corresponding setup time to clock (tIS) must be met. Also, a Deselect command must be

registered (with tIS set up time to clock) at clock edge Td. Once the CKE registered “High” after Reset, CKE needs to be

continuously registered “High” until the initialization sequence is finished, including expiration of tDLLK and tZQinit

4. The DDR4 SDRAM keeps its on-die termination in high-impedance state as long as RESET_n is asserted. Further, the SDRAM

keeps its on-die termination in high impedance state after RESET_n deassertion until CKE is registered HIGH. The ODT input

signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal

may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1 the ODT input signal must be statically held

LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration

of tDLLK and tZQinit.

5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load

mode register. (tXPR=Max(tXS, 5nCK)]

6. Issue MRS Command to load MR3 with all application settings( To issue MRS command to MR3, provide “Low” to BG0, “High” to

BA1, BA0)

7. Issue MRS command to load MR6 with all application settings (To issue MRS command to MR6, provide “Low” to BA0, “High” to

BG0, BA1)

8. Issue MRS command to load MR5 with all application settings (To issue MRS command to MR5, provide “Low” to BA1, “High” to

BG0, BA0)

9. Issue MRS command to load MR4 with all application settings (To issue MRS command to MR4, provide “Low” to BA1, BA0, “High”

to BG0)

10. Issue MRS command to load MR2 with all application settings (To issue MRS command to MR2, provide “Low” to BG0, BA0,

“High” to BA1)

11. Issue MRS command to load MR1 with all application settings (To issue MRS command to MR1, provide “Low” to BG0, BA1,

“High” to BA0)

12. Issue MRS command to load MR0 with all application settings (To issue MRS command to MR0, provide “Low” to BG0, BA1,

BA0)

13. Issue ZQCL command to starting ZQ calibration

14. Wait for both tDLLK and tZQ init completed

15. The DDR4 SDRAM is now ready for read/Write training (include Vref training and Write leveling).

--`,``,``,``,,```````,``,-`-``,```,,,`---

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