MT53E256M16D1：低功耗LPDDR4/LPDDR4X SDRAM技术规格

LPDDR4/LPDDR4X

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"MT53E256M16D1.pdf" 是一份关于 LPDDR4/LPDDR4X SDRAM 的技术规格文档，主要介绍了MT53E256M16D1和MT53E256M32D2这两种内存芯片的特性、工作电压、频率范围以及其它高级功能。该文档的关键知识点如下： 1. **低电压供电**：MT53E系列芯片具有超低电压核心和I/O电源，包括VDD1（1.70-1.95V，1.80V名义值）、VDD2（1.06-1.17V，1.10V名义值）以及两种VDDQ模式：标准模式（1.06-1.17V，1.10V名义值）和低电压模式（0.57-0.65V，0.60V名义值）。 2. **频率范围**：支持1866到10 MHz的工作频率，对应数据传输率范围为3733到20 Mbps/pin，这表明芯片能以高速进行数据传输。 3. **16n预取 DDR架构**：这种架构提高了数据处理效率，允许内存以更快的速度读写数据。 4. **并发操作**：每个通道有8个内部银行，可同时执行操作，增强了多任务处理能力。 5. **单数据速率CMD/ADR输入**：命令和地址输入采用单数据速率，简化了控制信号的处理。 6. **双向差分数据 strobe**：每个字节线路都有一个双向/差分数据 strobe，确保数据传输的准确性。 7. **可编程读写延迟**：RL（读延迟）和WL（写延迟）可以编程设置，以优化不同应用场景下的性能。 8. **可编程突发长度**：支持BL=16或32的突发长度，可以根据需要动态调整，提高内存利用率。 9. **按银行定向刷新**：允许并发银行操作，并简化命令调度。 10. **高带宽**：每个芯片的最高带宽可达8.5 GB/s，这在高速数据处理中至关重要。 11. **片上温度传感器**：用于监控温度并控制自刷新速率，确保在各种环境条件下稳定运行。 12. **部分数组自刷新**（PASR）：只刷新正在使用的内存部分，节省能源。 13. **可选输出驱动强度**（DS）：用户可以调整输出驱动强度以适应不同系统需求。 14. **时钟停止功能**：当不需要时钟信号时，可以暂停，进一步降低功耗。 15. **符合RoHS标准**：采用环保包装，不含有害物质。 16. **可编程VSS（ODT）终端**：输出端口的阻抗匹配可以通过编程来设定，以确保信号质量。 MT53E256M16D1和MT53E256M32D2是高性能、低功耗的LPDDR4/LPDDR4X SDRAM芯片，适用于需要高效数据处理和节能的现代电子设备，如智能手机、平板电脑和高性能计算平台。其特性涵盖了广泛的性能优化选项，以适应不同的系统配置和应用需求。

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Table 207: MR3 I/O Configuration 1 (MA[5:0] = 03h) ...................................................................................... 275

Table 208: MR3 Op-Code Bit Definitions ....................................................................................................... 276

Table 209: MR12 Register Information (MA[5:0] = 0Ch) .................................................................................. 277

Table 210: MR12 Op-Code Bit Definitions ...................................................................................................... 277

Table 211: Mode Register 14 (MA[5:0] = 0Eh) ................................................................................................. 277

Table 212: MR14 Op-Code Bit Definition ....................................................................................................... 278

Table 213: V

REF

Setting for Range[0] and Range[1] .......................................................................................... 279

Table 214: MR22 Register Information (MA[5:0] = 16h) ................................................................................... 280

Table 215: MR22 Register Information ........................................................................................................... 280

Table 216: Reference Voltage for

LZ(DQS),

HZ(DQS) Timing Measurements .................................................. 283

Table 217: Reference Voltage for

LZ(DQ),

HZ(DQ) Timing Measurements ..................................................... 285

Table 218: Internal V

REF(CA)

Specifications ..................................................................................................... 286

Table 219: Internal V

REF(DQ)

Specifications .................................................................................................... 287

Table 220: Pull-Down Driver Characteristics – ZQ Calibration ........................................................................ 289

Table 221: Pull-Up Characteristics – ZQ Calibration ....................................................................................... 289

Table 222: Terminated Valid Calibration Points .............................................................................................. 289

Table 223: Command Bus ODT State ............................................................................................................. 290

Table 224: ODT DC Electrical Characteristics for Command/Address Bus – up to 3200 Mbps ........................... 291

Table 225: ODT DC Electrical Characteristics for Command/Address Bus – Beyond 3200 Mbps ....................... 292

Table 226: ODT DC Electrical Characteristics for DQ Bus– up to 3200 Mbps .................................................... 293

Table 227: ODT DC Electrical Characteristics for DQ Bus – Beyond 3200 Mbps ............................................... 294

Table 228: Output Driver and Termination Register Sensitivity Definition ....................................................... 295

Table 229: Output Driver and Termination Register Temperature and Voltage Sensitivity ................................. 295

Table 230: Recommended DC Operating Conditions ..................................................................................... 297

Table 231: Single-Ended Output Slew Rate .................................................................................................... 297

Table 232: Differential Output Slew Rate ....................................................................................................... 298

Micron Confidential and Proprietary

200b: x32 LPDDR4/LPDDR4X SDRAM

Features

CCM005-554574167-10527

200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. B 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

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authorized representative.

General Description

The 8Gb Mobile Low-Power DDR4 SDRAM with low V

DDQ

(LPDDR4X) is a high-speed

CMOS, dynamic random-access memory. The device is internally configured with x16

I/O, 8-banks.

Micron Confidential and Proprietary

200b: x32 LPDDR4/LPDDR4X SDRAM

Important Notes and Warnings

CCM005-554574167-10527

200b_z00m_non-auto_lpddr4_lpddr4x.pdf – Rev. B 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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