深入学习ISE仿真器操作指南

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"ISE仿真器使用教程，深入介绍ISE仿真工具的使用和操作流程。" ISE仿真器，全称为Xilinx ISE Simulator，也被称为ISim，是Xilinx公司提供的一款强大的硬件描述语言（HDL）仿真工具。本教程旨在帮助用户全面理解和掌握ISE仿真器的使用方法和操作过程，以有效地进行FPGA或CPLD设计验证。本教程的内容可能包括以下几个方面： 1. **安装与设置**：首先，你需要了解如何下载和安装ISE仿真器，以及配置相关的环境变量，确保软件能够正常运行。 2. **项目创建**：在使用ISE仿真器之前，你需要学会创建一个新的工程，定义项目的时钟和其他系统参数，这通常是通过向导完成的。 3. **HDL代码导入与编译**：教程会讲解如何将Verilog或VHDL代码导入到项目中，并进行编译。编译过程包括语法检查、逻辑综合和生成网表等步骤。 4. **仿真环境搭建**：在ISim中，你需要配置仿真环境，如设置激励源（testbench），定义仿真时间范围，以及设置观察和分析信号的波形窗口。 5. **运行仿真**：学习如何启动仿真并观察仿真结果。ISim提供了多种仿真类型，如行为仿真、时序仿真等，用户可以根据需求选择合适的仿真模式。 6. **调试技巧**：教程会介绍如何使用ISim的调试工具，如断点设置、单步执行、查看变量值等功能，以便于找出设计中的错误。 7. **性能优化**：在仿真过程中，可能会遇到性能瓶颈，教程会指导用户如何分析仿真性能，优化代码以提高仿真速度。 8. **报告和分析**：学习如何解读仿真后的报告，如时序分析报告，理解设计的性能指标，以及如何根据报告进行设计调整。 9. **高级特性**：对于复杂的系统，可能涉及到并行仿真、多进程交互、内存模型等高级特性，教程会逐步解释这些功能的使用方法。 10. **问题解决**：教程通常会包含常见问题的解决方案，帮助用户解决在使用ISE仿真器过程中可能遇到的问题。请注意，Xilinx对提供的文档和资料拥有版权，未经许可不得擅自复制或分发。同时，Xilinx保留随时更新文档而不另行通知的权利，且不承担因技术支持或协助而可能导致的任何责任。用户在使用过程中应遵循Xilinx的条款和条件，以避免可能的法律风险。

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 3

UG682 (v1.0) April 27, 2009

Chapter 2

Using ISE Simulator from ISE Project

Navigator

Overview of ISim ISE Integrated Flow

The Xilinx

ISE software provides an integrated flow with the Xilinx ISE Simulator (ISim)

that allows simulations to be launched directly from the Xilinx Project Navigator (ISE). All

simulation commands that prepare the ISim simulation are generated by ISE Project

Navigator and automatically run in the background when simulating a design using this

flow.

Getting Started

Software Requirements

To use this tutorial, you must install the following software:

1. ISE WebPACK™ 11, or

2. One of the ISE Design Suite 11 Editions (Logic, DSP, Embedded, System)

For more information about installing Xilinx

software, see the ISE Release Notes and Installation

Guide at: http://www.xilinx.com/support/software_manuals.htm

Installing the Tutorial Design Files

Design files for this tutorial can be downloaded from:

http://www.xilinx.com/support/techsup/tutorials/tutorials11.htm

After you have downloaded the tutorial project files from the Web, unzip them into an

easily accessible directory with full read and write permissions.

The contents of the tutorial project files are as follows:

• sources: Folder containing all the HDL files necessary for a functional simulation of

the design.

• scripts: Folder containing incomplete script files to run the simulation. These script

files will be completed as you go through the tutorial.

• completed: Folder containing completed script, simulation and wave configuration

files, as well as a completed ISE 11 project of the tutorial design, for comparison

purposes.

4 www.xilinx.com ISE Simulator (ISim) In-Depth Tutorial

UG682 (v1.0) April 27, 2009

Design Description

The ISim In-Depth Tutorial provides a design which the reader can use to become familiar

performing some basic simulation steps while using the ISim software.

The tutorial design is a simple demonstration of the Dynamic Reconfiguration feature of

the Virtex

-5 Digital Clock Manager (DCM).

Using the Virtex-5 DCM, the design generates an output clock using the following

relationship:

Output Clock = Input Clock * (Multiplier / Divider)

Using the Dynamic Reconfiguration Ports (DRP) in the DCM, the design allows the user to

re-define the Multiplier and Divider parameters to generate different output frequencies.

Functional Blocks

The tutorial design consists of the following functional blocks.

• drp_dcm (drp_dcm.vhd)

Virtex-5 DCM macro with internal feedback, frequency controlled output, duty-cycle

correction, and Dynamic Reconfiguration ability.

The CLKFX_OUT output provides a clock that is defined by the following

relationship:

CLKFX_OUT = CLKIN_IN * (Multiplier/Divider)

For example, using a 100 MHz input clock, setting the Multiplier factor to 6, and

Divider factor to 5, produces a 120 MHz CLKFX_OUT output clock.

Using the DRP ports of the DCM, the Multiplier (M) and Divider (D) parameters can

be dynamically redefined to produce different CLKFX_OUT frequencies. For the

purposes of this tutorial, it suffices to show how the Multiply and Divide parameters

are provided to the DCM via the 16-bit wide DI_IN port:

DI_IN[15:8] = M – 1

DI_IN[7:0] = D – 1

For example, for an M/D factor of 6 / 5, DI_IN = 0504h.

• drp_stmach (drp_stmach.vhd)

This module describes a Dynamic Reconfiguration Controller. The DRP controller

asserts and monitors the DCM DRP signals in order to perform a dynamic

reconfiguration cycle.

A dynamic reconfiguration cycle is started by asserting the drp_start signal. Following

this step, the DRP Controller asserts the appropriate DCM DRP pins in order to

complete a full Dynamic Reconfiguration cycle.

Signal drp_done indicates a successful completion of a dynamic reconfiguration cycle.

• drp_demo (drp_demo.vhd)

This is the top module of the tutorial design which connects the DCM macro and the

DRP controller modules to the external I/O ports.

• drp_demo_tb (drp_demo_tb.vhd)

Self-checking HDL test bench. Refer to Design Self-Checking Test Bench for more

information.

ISE Simulator (ISim) In-Depth Tutorial www.xilinx.com 5

UG682 (v1.0) April 27, 2009

Simulating the Design

Design Self-Checking Test Bench

To test the functionality of this design, a self-checking test bench has been provided. (Refer to

source file drp_demo_tb.vhd in the sources folder.) A self-checking test bench contains a validation

routine or function that compares sampled values from the simulation against expected results. The

self-checking test bench provided for this design performs the following functions.

• Generates a 100 MHz input clock for the design system clock (clk_in).

• Performs four different tests in order to dynamically change the output frequency of

the design. In each test, a DRP cycle is started (using the drp_start signal) to set the

output clock to a different frequency. The following table shows the desired output

frequency and Multiplier/Divider parameters used for each test.

• In each test, the test bench will compare the expected clock period and the clock period

measured during simulation. Based on the comparison results, messages to the simulator will

be written indicating success or failure.

• Upon completion of the simulation, a summary report is provided, listing which tests

passed or failed.

Note:

For more details on the functionality of this design, refer to the in-line comments included in

the sources of the design.

Simulating the Design

Thanks to an intuitive integrated flow, you can easily and quickly perform behavioral and

timing simulations of your design in the ISE Project Navigator software. Using the

integrated flow, you can quickly set up simulation properties and launch the ISim software

with a few clicks of the mouse.

We shall demonstrate how ISim can be launched using the ISE Project Navigator by first

creating an ISE project for the tutorial design. We will then set some behavioral simulation

properties and launch the ISim simulator to perform a behavioral simulation of the design.

Creating a Project in ISE Project Navigator

We will use the New Project Wizard in ISE Project Navigator to quickly create an ISE

project for the tutorial design.

Note:

Read Installing the Tutorial Design Files to obtain the files required for this design.

Using New Project Wizard

Follow these steps to create an ISE project using the New Project Wizard.

1. Launch the ISE Project Navigator by double-clicking on the Xilinx ISE 11 desktop icon.

Table 2-1: Desired Output Frequency and Multiplier/Divider Parameters Used For

Each Test

Test Freq. (MHz) Period (ps) Multiplier (M) Divider (D)

17513,3323 4

2 120 8,332 6 5

3 250 4000 5 2

4 400 2,500 4 1

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