HDMI 2.1 接口转换驱动器：TI TDP1204 高速信号增强解决方案

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"TI-TDP1204.pdf是一款12-Gbps HDMI转接驱动器，适用于HDMI 2.1标准，支持最高达12Gbps的数据速率，并兼容HDMI 1.4和2.0b标准。该器件集成了AC/DC耦合输入和输出，具备可编程接收均衡器、I2C控制、HPD电平转换器、DDC缓冲器等功能，适用于笔记本、台式机、电视、家庭娱乐系统、游戏系统、坞站以及专业音频、视频和标牌等多种应用场景。" TI公司的TDP1204是一款高性能的HDMI转接驱动器，旨在满足现代高清数字传输的需求。这款器件的最大亮点在于其对HDMI 2.1标准的支持，能够处理高达12Gbps的数据速率，同时向下兼容HDMI 1.4和2.0b标准，确保了与各种设备的广泛兼容性。HDMI 2.1标准引入了固定速率链接（FRL），TDP1204支持3.6Gbps、6Gbps、8Gbps、10Gbps和12Gbps五种不同速率，且能处理三线和四线FRL模式，适应不同的传输需求。为了优化HDMI源应用，TDP1204配备了可编程接收均衡器，最大提升幅度可达12dB，频率高达6GHz，有助于改善信号质量，尤其是在长距离传输或复杂布线环境下的信号完整性。此外，通过I2C接口，用户可以进行内部设置，实现更加精确的信号调整。集成的HPD（High-Speed Port Data）电平转换器支持1.8V和3.3V LVCMOS电平，确保与不同电压标准的设备无缝对接。DDC（Digital Display Control）缓冲器则可以支持低至1.2V的电平，增强了电源管理的灵活性。器件还具有完整的主通道切换功能，以适应不同的连接需求。在功耗方面，TDP1204表现出色，当12Gbps FRL四通道活跃时，有限模式下功耗仅为575mW，线性模式下则为220mW，而在功率下降模式下，功耗降低到0.6mW，这使得它非常适合对能耗敏感的应用。同时，该器件可在商业和工业温度范围内稳定工作，采用单3.3V电源供电，封装为40引脚、0.4mm间距、4mm×6mm的WQFN封装，尺寸紧凑，易于集成到各类产品设计中。 TI的TDP1204是HDMI 2.1系统设计的理想选择，它结合了高效的数据处理能力、灵活的配置选项和低功耗特性，适用于多种应用场景，包括但不限于笔记本电脑、桌面电脑、电视、家庭影院系统、游戏主机、坞站、专业音频、视频设备以及数字标牌等。

6.5 Electrical Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

HF-

TXSWG-R

High-frequency 1-dB compression point

Dx_VOD = 1.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12Gbps CTLE;

CTLEBYP_EN = 0;TX DC coupled to

VCC_EXT;

800 mVpp

LF-

TXSWG-F

Low-frequency 1-dB compression point

Dx_VOD = 2.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps; TX DC coupled to

VCC_EXT;

1100 mVpp

HF-

TXSWG-F

High-frequency 1-dB compression point

Dx_VOD = 2.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;

CTLEBYP_EN = 0; TX DC coupled to

VCC_EXT;

875 mVpp

LF-

TXSWG-1

Low-frequency 1-dB compression point

Dx_VOD = 3.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps; TX DC coupled to

VCC_EXT;

1200 mVpp

HF-

TXSWG-1

High-frequency 1-dB compression point

Dx_VOD = 3.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;

CTLEBYP_EN = 0; TX DC coupled to

VCC_EXT;

950 mVpp

6.6 Timing Requirements

MIN NOM MAX UNIT

Local I2C (SCL/CFG0, SDA/CFG1). Refer to Figure 7-9.

SCL

C clock frequency 1 MHz

BUF

Bus free time between START and STOP conditions 0.5 µs

HD_STA

Hold time after repeated START condition. After this period, the first clock

pulse is generated

0.26 µs

LOW

Low period of the I

C clock 0.5 µs

HIGH

High period of the I

C clock 0.26 µs

SU_STA

Setup time for a repeated START condition 0.26 µs

HD_DAT

Data hold time 0 μs

SU_DAT

Data setup time 50 ns

Rise time of both SDA and SCL signals 120 ns

Fall time of both SDA and SCL signals 4 120 ns

SU_STO

Setup time for STOP condition 0.26 μs

DDC Snoop I2C Timings. Refer to Figure 7-9.

SCL

C DDC clock frequency 100 kHz

BUF

Bus free time between START and STOP conditions 4.7 µs

HD_STA

Hold time after repeated START condition. After this period, the first clock

pulse is generated

4 µs

LOW

Low period of the I

C clock 4.7 µs

HIGH

High period of the I

C clock 4 µs

SU_STA

Setup time for a repeated START condition 4.7 µs

HD_DAT

Data hold time 0 μs

SUDAT

Data setup time 250 ns

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6.6 Timing Requirements (continued)

MIN NOM MAX UNIT

Rise time of both SDA and SCL signals. Measured from 30% to 70%. 1000 ns

Fall time of both SDA and SCL signals Measured from 70% to 30%. 300 ns

SU_STO

Setup time for STOP condition 4 μs

b_LV

Capacitive load for each bus line on LV side 50 pF

Power-On. Refer to Figure 7-1.

VCC_RAMP

supply ramp. Measured from 10% to 90%. 0.10 50 ms

D_PG

Internal POR de-assertion delay 5 ms

VIO_SU

supply stable before reset

(2)

high. 100 µs

CFG_SU

Configuration pins

(1)

setup before reset

(2)

high. 0 µs

CFG_HD

Configuration pins

(1)

hold after reset

(2)

high. 500 µs

(1) Follow comprise the configuration pins: MODE, ADDR/EQ0, EQ1, TXSWG, TXSLEW, TXPRE, AC_EN, HPDOUT_SEL, DCGAIN

(2) Reset is the logical AND of internal POR and EN pin.

6.7 Switching Characteristics

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Redriver

HDMI14_o

pen

Maximum HDMI 1.4 clock frequency at

which TX termination is assured to be

open

HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz;

TXTERM_AUTO_HDMI14 = 0h; TERM =

2h; TX is DC-coupled;

165 MHz

HDMI14_3

Minimum HDMI 1.4 clock frequency at

which TX termination is assured to be

300-ohms

HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340 MHz;

TXTERM_AUTO_HDMI14 = 0h; TERM =

2h; TX is DC-coupled;

250 MHz

AEQ_DON

Time from start of FRL link training to

AEQ complete for 3 Gbps.

0.7 ms

AEQ_DON

Time from start of FRL link training to

AEQ complete for 6 Gbps, 8 Gbps, 10

Gbps, and 12 Gbps

0.5 ms

Propagation delay time At TTP4; 90 220 ps

SK1(T)

Data lane Intra-pair output skew with

worse case skew at inputs

At TTP4; With 0.15 UI skew at input; At

12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX

termination 100-Ω; Linear mode;

0.15 UI

SK1(T)

Clock lane Intra-pair output skew with

zero intra-pair skew at inputs

At TTP4; No intra-pair skew at input; 6

Gbps with 150 MHz clock; TX termination

100-Ω; Limited mode;

0.10 0.15 UI

SK1(T)

Data lane Intra-pair output skew with zero

intra-pair skew at inputs

At TTP4; No intra-pair skew at input; At

12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX

termination 100-Ω; Limited mode;

0.053 0.11 UI

SK2(T)

Inter-pair output skew

At TTP4; At 12 Gbps; LTP5, 6, 7, or 8;

TXFFE0;

30 ps

RF-CLK-14

Transition time (rise and fall time) for

clock lane when operating at HDMI1.4

At TTP4; 20% to 80%; Clock Frequency =

300 MHz;

75 600 ps

RF-CLK-20

Transition time (rise and fall time) for

clock lane when operating at HDMI 2.0

At TTP4; 20% to 80%; Clock Frequency =

150 MHz;

75 600 ps

RF_14

Transition time (rise and fall time) for data

lanes when operating at HDMI 1.4

At TTP4; 20% to 80%; DR = 3

Gbps; SLEW_HDMI14 = default; PRBS7

pattern; Clock Frequency = 300 MHz;

75 195 ps

RFDAT_20

Transition time (rise and fall time) for data

lanes when operating at HDMI 2.0

At TTP4; 20% to 80%; DR = 6

Gbps; SLEW_HDMI20 = default; PRBS7

pattern; Clock Frequency = 150 MHz;

42.5 115 ps

TDP1204

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6.7 Switching Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SLEW_FRL

Single-ended TX slew rate for data lanes

when operating at HDMI 2.1 FRL

At TTP4; Slope at 50% level; All FRL DR

up to 12 Gbps; SLEW_HDMI21 = Default;

clock pattern of 128 zeros and 128 ones;

16 mV/ps

TRANS_3G

Transistion bit duration when de-

emphasis/pre-emphasis is enabled

At TTP4; DR = 3 Gbps; Clock pattern of

128 zeros followed by 128 ones;

0.4 1 UI

TRANS_6G

Transistion bit duration when de-

emphasis/pre-emphasis is enabled

At TTP4; DR = 6 Gbps; Clock pattern of

128 zeros followed by 128 ones;

0.4 1 UI

TRANS_8G

Transistion bit duration when de-

emphasis/pre-emphasis is enabled

At TTP4; DR = 8 Gbps; Clock pattern of

128 zeros followed by 128 ones;

0.4 1 UI

TRANS_10

Transistion bit duration when de-

emphasis/pre-emphasis is enabled

At TTP4; DR = 10 Gbps; Clock pattern of

128 zeros followed by 128 ones;

0.5 1.1 UI

TRANS_12

Transistion bit duration when de-

emphasis/pre-emphasis is enabled

At TTP4; DR = 12 Gbps; Clock pattern of

128 zeros followed by 128 ones;

0.6 1.3 UI

HPD

HPD_PD

HPD_IN to HPD_OUT propagation delay Refer to Figure 7-7 100 µs

HPD_PWR

DOWN

HPD_IN debounce time before declaring

Powerdown. Enter Powerdown if

HPD_IN is low after debounce time.

Refer to Figure 7-7 2 4 ms

HPD_STAN

DBY

HPD_IN debounce time required for

exiting Powerdown to Standby. Exit

Powerdown if HPD_IN is high after

debounce time.

Refer to Figure 7-8 2 4 ms

Standby

STANDBY_

ENTRY

Detection of electrical idle to entry into

Standby.

HPD_IN = H; 300 µs

SIGDET_D

Maximum differential signal glitch

time rejected during debounce before

transitioning from standby to active

HPD_IN = H; 25 µs

SIGDET_D

Maximum differential signal glitch

time rejected during debounce before

transitioning from active to standby

HPD_IN = H; 50 ns

STANDBY_

EXIT

Detection of differential signal to exit from

Standby to Active state

HPD_IN = H; Does not include AEQ time

if AEQ_TX_DELAY_EN = 1;

200 µs

DDC Buffer

SCL

DDC buffer frequency 100 kHz

PLH1

Propagation delay time. Low-to-high-level

output. VIO set to 1.2 V LVCMOS levels.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1400 ns

Propagation delay time. Low-to-high-level

output. VIO set to 1.8 V LVCMOS levels.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1400 ns

Propagation delay time. Low-to-high-level

output. VIO set to 3.3 V LVCMOS levels.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1400 ns

PLH2

Propagation delay time. Low-to-high-level

output. VIO set to 1.2 V LVCMOS levels.

HV to LV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

410 ns

Propagation delay time. Low-to-high-level

output. VIO set to 1.8 V LVCMOS levels.

HV to LV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

410 ns

Propagation delay time. Low-to-high-level

output. VIO set to 3.3 V LVCMOS levels.

HV to LV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

410 ns

PHL1

Propagation delay time. High to low-level

output. VIO set to 1.2 V LVCMOS.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1200 ns

Propagation delay time. High to low-level

output. VIO set to 1.8 V LVCMOS.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1200 ns

Propagation delay time. High to low-level

output. VIO set to 3.3 V LVCMOS.

LV to HV; C

LV_BUS

= C

HV_BUS

= 50 pF;

DDC_LV_DCC_EN = 1'b1;

1200 ns

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