CS
SC
SO
t
3
t
2
t
4
t
1
t
4
t
r
t
f
5
LM95071
www.ti.com
SNIS137G –AUGUST 2004–REVISED AUGUST 2019
Product Folder Links: LM95071
Submit Documentation FeedbackCopyright © 2004–2019, Texas Instruments Incorporated
Logic Electrical Characteristics - Digital DC Characteristics (continued)
Unless otherwise noted, these specifications apply for V
DD
= 2.4 V to 5.5 V
(1)
.
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
UNIT
Input Hysteresis
Voltage
V
DD
= 3 V to 3.6 V
T
A
= T
J
= +25°C 0.4
V
T
A
= T
J
= T
MIN
to T
MAX
0.33
I
IN(1)
Logical “1” Input
Current
V
IN
= V
DD
T
A
= T
J
= +25°C 0.005
µA
T
A
= T
J
= T
MIN
to T
MAX
3
I
IN(0)
Logical “0” Input
Current
V
IN
= 0 V
T
A
= T
J
= +25°C −0.005
µA
T
A
= T
J
= T
MIN
to T
MAX
−3
C
IN
All Digital Inputs T
A
= T
J
= +25°C 20 pF
V
OH
High Level
Output Voltage
I
OH
= −400 µA, T
A
= T
J
= T
MIN
to T
MAX
2.25 V
V
OL
Low Level
Output Voltage
I
OL
= +1.6 mA, T
A
= T
J
= T
MIN
to T
MAX
0.4 V
I
O_TRI-
STATE
TRI-STATE
®
Output
Leakage Current
V
O
= GND
V
O
= V
DD
, T
A
= T
J
= T
MIN
to T
MAX
−1 +1 µA
(1) The of the LM95071 will operate properly over the V
DD
supply voltage range of 2.4V to 5.5V.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(3) Typicals are at T
A
= 25°C and represent most likely parametric norm.
6.7 Logic Electrical Characteristics - Serial Bus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
DD
= 2.4 V to 5.5 V
(1)
; C
L
(load capacitance) on output lines = 100 pF
unless otherwise specified.
MIN
(2)
TYP
(3)
MAX
(2)
UNIT
t
1
SC (Clock) Period
T
A
= T
J
= T
MIN
to T
MAX
0.16
µs
T
A
= T
J
= +25°C DC
t
2
CS Low to SC (Clock) High Set-Up Time T
A
= T
J
= T
MIN
to T
MAX
100 ns
t
3
CS Low to Data Out (SO) Delay T
A
= T
J
= T
MIN
to T
MAX
70 ns
t
4
SC (Clock) Low to Data Out (SO) Delay T
A
= T
J
= T
MIN
to T
MAX
70 ns
t
5
CS High to Data Out (SO) TRI-STATE T
A
= T
J
= T
MIN
to T
MAX
200 ns
t
6
SC (Clock) High to Data In (SI) Hold Time T
A
= T
J
= T
MIN
to T
MAX
50 ns
t
7
Data In (SI) Set-Up Time to SC (Clock)
High
T
A
= T
J
= T
MIN
to T
MAX
30 ns
t
8
SC (Clock) High to CS High Hold Time T
A
= T
J
= T
MIN
to T
MAX
50 ns
6.8 Timing Diagrams
Figure 1. Data Output Timing Diagram
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