Version 1.2 Specification for D-PHY
01-Aug-2014
4 D-PHY Overview
D-PHY describes a source synchronous, high speed, low power, low cost PHY, especially suited for mobile
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applications. This D-PHY specification has been written primarily for the connection of camera and display
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applications to a host processor. Nevertheless, it can be applied to many other applications. It is envisioned
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that the same type of PHY will also be used in a dual-simplex configuration for interconnections in a more
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generic communication network. Operation and available data-rates for a Link are asymmetrical due to a
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master-slave relationship between the two sides of the Link. The asymmetrical design significantly reduces
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the complexity of the Link. Some features like bi-directional, half-duplex operation are optional. Exploiting
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this feature is attractive for applications that have asymmetrical data traffic requirements and when the cost
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of separate interconnects for a return channel is too high. While this feature is optional, it avoids mandatory
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overhead costs for applications that do not have return traffic requirements or want to apply physically
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distinct return communication channels.
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4.1 Summary of PHY Functionality
The D-PHY provides a synchronous connection between Master and Slave. A practical PHY Configuration
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consists of a clock signal and one or more data signals. The clock signal is unidirectional, originating at the
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Master and terminating at the Slave. The data signals can either be unidirectional or bi-directional
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depending on the selected options. For half-duplex operation, the reverse direction bandwidth is one-fourth
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of the forward direction bandwidth. Token passing is used to control the communication direction of the
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Link.
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The Link includes a High-Speed signaling mode for fast-data traffic and a Low-Power signaling mode for
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control purposes. Optionally, a Low-Power Escape mode can be used for low speed asynchronous data
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communication. High speed data communication appears in bursts with an arbitrary number of payload
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data bytes.
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The PHY uses two wires per Data Lane plus two wires for the Clock Lane. This gives four wires for the
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minimum PHY configuration. In High-Speed mode each Lane is terminated on both sides and driven by a
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low-swing, differential signal. In Low-Power mode all wires are operated single-ended and non-terminated.
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For EMI reasons, the drivers for this mode shall be slew-rate controlled and current limited.
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The actual maximum achievable bit rate in High-Speed mode is determined by the performance of
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transmitter, receiver and interconnect implementations. Therefore, the maximum bit rate is not specified in
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this document. However, this specification is primarily intended to define a solution for a bit rate range of
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80 to 1500 Mbps per Lane without deskew calibration and up to 2500 Mbps with deskew calibration. When
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the DUT supports a data rate greater than 1500 Mbps, it shall also support deskew capability. Although
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PHY Configurations are not limited to this range, practical constraints make it the most suitable range for
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the intended applications. For a fixed clock frequency, the available data capacity of a PHY Configuration
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can be increased by using more Data Lanes. Effective data throughput can be reduced by employing burst
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mode communication. The maximum data rate in Low-Power mode is 10 Mbps.
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4.2 Mandatory Functionality
All functionality that is specified in this document and which is not explicitly stated in Section 5.5 shall be
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implemented for all D-PHY configurations.
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