JESD79E
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Burst Type
Accesses within a given burst may be pro-
grammed to be either sequential or interleaved; this
is referred to as the burst type and is selected via bit
A3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 3.
Read Latency
The READ latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. For
DDR200, DDR266, and DDR333, the latency can
be set to 2 or 2.5 clocks (latencies of 1.5 or 3 are op-
tional, and one or both of these optional latencies
might be supported by some vendors). For
DDR400, the latency can be set to 3 clocks (laten-
cies of 2 or 2.5 are optional, and one or both of these
optional latencies might be supported by some ven-
dors).
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m.
Reserved states should not be used as unknown
operation, or incompatibility with future versions
may result.
Operating Mode
The normal operating mode is selected by issuing
a Mode Register Set command with bits A7--A13
each set to zero, and bits A0--A6 set to the desired
values. A DLL reset is initiated by issuing a Mode
Register Set command with bits A7 and A9--A13
each set to zero, bit A8 set to one, and bits A0--A6
set to the desired values. A Mode Register Set com-
mand issued to reset the DLL must always be fol-
lowed by a Mode Register Set command to select
normal operating mode (i.e., with A8=0).
All other combinations of values for A7--A13 are
reserved for future use and/or test modes. Test
modes and reserved states should not be used be-
cause unknown operation or incompatibility with fu-
ture versions may result.
Terminology Definitions.
The following are definitions of the terms
DDR200, DDR266, & DDR333, as used in this
specification.
DDR200: A speed grade for DDR SDRAM devices.
The nominal operating (clock) frequency of such
devices is 100 MHz (meaning that although the de-
vices operate over a range of clock frequencies, the
timing specifications included in this speed grade
are tailored to a 100 MHz clock frequency). The cor-
responding nominal data rate is *200 MHz.
DDR266: A Speed grade for DDR SDRAM devices.
The nominal operating (clock) frequency of such
devices is 133 MHz (meaning that although the de-
vices operate over a range of clock frequencies, the
timing specifications included in this speed grade
are tailored to a 133 MHz clock frequency). The cor-
responding nominal data rate is *266 MHz.
DDR333: A Speed grade for DDR SDRAM devices.
The nominal operating (clock) frequency of such
devices is 167 MHz (meaning that although the de-
vices operate over a range of clock frequencies, the
timing specifications included in this speed grade
are tailored to a 167 MHz clock frequency). The cor-
responding nominal data rate is *333 MHz.
DDR400: A Speed grade for DDR SDRAM devices.
The nominal operating (clock) frequency of such
devices is 200 MHz (meaning that although the de-
vices operate over a range of clock frequencies, the
timing specifications included in this speed grade
are tailored to a 200 MHz clock frequency). The cor-
responding nominal data rate is *400 MHz.
In addition to the above DDRxxx specification, a let-
ter modifier may be applied to indicate special tim-
ing characteristics for these devices in various mar-
ket applications. For example, DDR266A and
DDR266B classifications define distinct sorts for
operation as a function of CAS latency. These differ-
ences between sorts are described in Table 12, ”AC
T iming Variations”.
* In this context, the term MHz is used loosely. A
more technically precise definition is ”million trans-
fers per second per data pin”