ATMEL E2PROM 读写操作与特性详解

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"ATMEL E2prom 读写时序以及说明" ATMEL E2prom，即电可擦除可编程只读存储器，是一种非易失性存储技术，适用于需要频繁读写且在断电后仍能保持数据的应用。AT24C01A/02/04/08/16是ATMEL公司推出的一系列E2prom芯片，它们提供不同容量的存储空间，分别为1K、2K、4K、8K和16K位，每个位对应8位的数据宽度。这些设备主要设计用于工业和商业应用，尤其在低功耗和低电压操作的场景下表现出色。这些E2prom芯片具备以下关键特性： 1. **电压范围广泛**：支持5.0V（标准电压）、2.7V、2.5V和1.8V的电源电压，适应多种工作环境。 2. **两线串行接口**：采用I2C（Inter-Integrated Circuit）协议，只需要两根线（SCL和SDA）即可实现数据的双向传输，简化了硬件设计。 3. **施密特触发器和滤波输入**：提高信号抗噪声能力，确保数据传输的可靠性。 4. **写保护引脚**：硬件级别的数据保护，防止意外修改。 5. **页写模式**：8字节（1K、2K）或16字节（4K、8K、16K）的页写模式，允许快速写入大量数据。 6. **部分页写允许**：无需完整页写入，可以进行部分数据更新。 7. **自定时写周期**：最大10毫秒的写周期，由内部计时器控制，简化了系统设计。 8. **高可靠性**：百万次的写耐久性和100年的数据保留时间，保证了长期稳定的数据存储。 9. **汽车级和扩展温度设备**：提供适用于恶劣环境的版本，如汽车行业的宽温范围应用。 10. **封装形式多样**：包括8引脚JEDC SOIC、8引脚PDIP和8引脚TSSOP封装，满足不同应用场景的需求。读写时序是理解ATMEL E2prom操作的关键。读操作通常包括开始条件、地址发送、数据接收和停止条件。写操作则涉及开始条件、地址发送、数据写入和可能的应答，最后是停止条件。具体时序需要遵循I2C协议，包括时钟同步、数据采样和释放规则。在写操作中，写保护引脚的状态会决定是否允许写入，如果被激活，则写操作将被禁止。 ATMEL E2prom系列芯片因其灵活性、可靠性和低功耗特性，广泛应用于各种嵌入式系统、传感器记录、配置存储、设备标识等多种场合。了解其读写时序和特性对于正确地在系统中集成和有效利用这些存储器至关重要。

AT24C01A/02/04/08/16

Note: 1. This parameter is characterized and is not 100% tested.

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-

mally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL

high periods will indicate a start or stop condition as

defined below.

START CONDITION: A high-to-low transition of SDA with

SCL high is a start condition which must precede any

other command (refer to Start and Stop Definition timing

diagram).

STOP CONDITION: A low-to-high transition of SDA with

SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power

mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are seri-

ally transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a zero to acknowledge that it has

received each word. This happens during the ninth clock

cycle.

STANDBY MODE: The AT24C01A/02/04/08/16 features a

low-power standby mode which is enabled: (a) upon

power-up and (b) after the receipt of the STOP bit and the

completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power

loss or system reset, any 2-wire part can be reset by follow-

ing these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

AC Characteristics

Applicable over recommended operating range from T

= -40°C to +85°C, V

= +1.8V to +5.5V, CL = 1 TTL Gate and

100 pF (unless otherwise noted).

Symbol Parameter

2.7-, 2.5-, 1.8-volt 5.0-volt

UnitsMin Max Min Max

SCL

Clock Frequency, SCL 100 400 kHz

LOW

Clock Pulse Width Low 4.7 1.2 µs

HIGH

Clock Pulse Width High 4.0 0.6 µs

Noise Suppression Time

(1)

100 50 ns

Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs

BUF

Time the bus must be free before

a new transmission can start

(1)

4.7 1.2 µs

HD.STA

Start Hold Time 4.0 0.6 µs

SU.STA

Start Setup Time 4.7 0.6 µs

HD.DAT

Data In Hold Time 0 0 µs

SU.DAT

Data In Setup Time 200 100 ns

Inputs Rise Time

(1)

1.0 0.3 µs

Inputs Fall Time

(1)

300 300 ns

SU.STO

Stop Setup Time 4.7 0.6 µs

Data Out Hold Time 100 50 ns

Write Cycle Time 10 10 ms

Endurance

(1)

5.0V, 25°C, Byte Mode 1M 1M Write

Cycles

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