【免费】pcie-3.0-总线规范_pcie5.0

pcie

需积分: 0 24 浏览量更新于2024-01-09 评论 2 收藏 4.83MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

PCIE-3.0总线规范，即PCI Express® Base Specification Revision 3.0，是一项关于计算机总线规范的技术标准。最初发布于2002年7月22日，随后于2003年4月15日进行了错误更正，2005年3月28日进行了修订，2006年12月20日增加了数据速率为5.0 GT/s，并对错误进行了修正。 PCI Express（简称PCIe）是一种用于连接计算机内部组件的总线技术。它是一种串行总线，用于替代传统的并行PCI总线，提供更高的数据传输速率和更低的功耗。PCIe-3.0是PCIe总线规范的第三个主要版本，是在PCIe-2.0的基础上进行改进的。 PCIe-3.0引入了5.0 GT/s的数据传输速率，相比于PCIe-2.0的2.5 GT/s，传输速度提高了一倍。这使得PCIe总线能够更好地满足高性能计算和数据传输的需求。此外，PCIe-3.0还进行了一系列的错误更正和功能增强，以提供更可靠和高效的数据传输。 PCIe-3.0的错误更正和增强功能主要通过Errata和ECN（Engineering Change Notice）来实现。Errata是对规范中已知错误的更正，ECN是对规范中功能的增强或改进。这些更正和增强功能的目的是提高PCIe总线的性能和可靠性，同时保持与之前版本的向后兼容性。 PCIe总线规范的修订历史体现了PCIe技术的不断演进和改进。初版的PCIe-1.0于2002年发布，为计算机组件之间的连接提供了一种新的解决方案。随着技术的发展和需求的增加，PCIe-2.0在2006年推出，提供了更高的传输速率和扩展性。最新的PCIe-3.0标准于2010年发布，继续改进和提高了传输速率和功能。综上所述，PCIe-3.0总线规范是一项关键的技术标准，用于计算机内部组件之间的高速数据传输。它提供了更高的传输速率、更可靠的性能和更低的功耗，为高性能计算和数据传输应用提供了有效的解决方案。通过不断的错误更正和功能增强，PCIe-3.0规范保持了与之前版本的兼容性，并不断适应技术的发展和市场的需求。

资源详情

资源评论

资源推荐

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE......................................... 546

FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES................................................... 564

FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 568

IGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT.................................................. 569

IGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS...................................................... 571

FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY

MESSAGES ........................................................................................................................... 572

FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 576

IGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 576

IGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 577

FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER............................................................ 588

FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER................................................................ 595

FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER................................................................ 597

IGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER..................................................... 601

IGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 602

FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 603

FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE................................................................. 605

FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 605

FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 606

FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 608

FIGURE 7-14: DEVICE CONTROL REGISTER................................................................................. 613

FIGURE 7-15: DEVICE STATUS REGISTER.................................................................................... 620

FIGURE 7-16: LINK CAPABILITIES REGISTER............................................................................... 622

FIGURE 7-17: LINK CONTROL REGISTER..................................................................................... 627

FIGURE 7-18: LINK STATUS REGISTER........................................................................................ 635

FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 638

FIGURE 7-20: SLOT CONTROL REGISTER..................................................................................... 640

FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 644

FIGURE 7-22: ROOT CONTROL REGISTER.................................................................................... 646

FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 647

IGURE 7-24: ROOT STATUS REGISTER....................................................................................... 648

FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER........................................................................ 649

IGURE 7-26: DEVICE CONTROL 2 REGISTER.............................................................................. 654

IGURE 7-27: LINK CAPABILITIES 2 REGISTER............................................................................ 658

FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 660

FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 665

IGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT.................................. 668

FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 669

IGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE

............................................................................................................................................. 671

FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER........................ 672

IGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER........................................................ 673

FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER........................................................... 675

IGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER..................................................... 677

IGURE 7-37: CORRECTABLE ERROR STATUS REGISTER............................................................. 679

IGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 680

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 681

FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 683

FIGURE 7-41: ROOT ERROR COMMAND REGISTER...................................................................... 683

IGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 685

IGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 687

FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 688

FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 689

FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 690

IGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 691

IGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 692

FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 693

FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 694

FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER.................................................................. 695

IGURE 7-52: VC RESOURCE CONTROL REGISTER...................................................................... 697

IGURE 7-53: VC RESOURCE STATUS REGISTER......................................................................... 699

FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES........................................... 701

FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES

............................................................................................................................................. 702

FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 703

FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER.................................. 704

FIGURE 7-58: SERIAL NUMBER REGISTER................................................................................... 705

FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 706

FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER............... 707

FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 708

FIGURE 7-62: LINK ENTRY.......................................................................................................... 709

FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 709

FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0.......................................................................... 711

FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1.......................................................................... 712

FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY...................................... 713

FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER...................... 713

IGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 714

FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 717

IGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 719

IGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE................................. 720

FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER.......................................... 721

FIGURE 7-73: POWER BUDGETING DATA REGISTER.................................................................... 722

IGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 724

FIGURE 7-75: ACS EXTENDED CAPABILITY................................................................................ 725

IGURE 7-76: ACS EXTENDED CAPABILITY HEADER ................................................................. 725

FIGURE 7-77: ACS CAPABILITY REGISTER ................................................................................. 726

FIGURE 7-78: ACS CONTROL REGISTER ..................................................................................... 727

IGURE 7-79: EGRESS CONTROL VECTOR REGISTER................................................................... 730

FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY......... 731

IGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED

CAPABILITY HEADER........................................................................................................... 731

IGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE..................................................... 733

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER.............................................................. 733

FIGURE 7-84: PORT VC CAPABILITY REGISTER 1 ....................................................................... 734

FIGURE 7-85: PORT VC CAPABILITY REGISTER 2 ....................................................................... 736

IGURE 7-86: PORT VC CONTROL REGISTER .............................................................................. 737

IGURE 7-87: PORT VC STATUS REGISTER ................................................................................. 738

FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER.................................................................. 738

FIGURE 7-89: VC RESOURCE CONTROL REGISTER...................................................................... 740

FIGURE 7-90: VC RESOURCE STATUS REGISTER......................................................................... 742

IGURE 7-91: PCI EXPRESS VSEC STRUCTURE.......................................................................... 746

IGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 746

FIGURE 7-93: VENDOR-SPECIFIC HEADER .................................................................................. 747

FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE........................................... 748

FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 748

IGURE 7-96: VENDOR ID AND DEVICE ID ................................................................................. 749

IGURE 7-97: RCRB CAPABILITIES ............................................................................................ 750

FIGURE 7-98: RCRB CONTROL................................................................................................... 750

FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE................................................. 751

FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER .................................................... 751

FIGURE 7-101: MULTICAST CAPABILITY REGISTER .................................................................... 752

FIGURE 7-102: MULTICAST CONTROL REGISTER ........................................................................ 753

FIGURE 7-103: MC_BASE_ADDRESS REGISTER ......................................................................... 754

FIGURE 7-104: MC_RECEIVE REGISTER ..................................................................................... 754

FIGURE 7-105: MC_BLOCK_ALL REGISTER............................................................................... 755

FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER............................................................ 756

FIGURE 7-107: MC_OVERLAY_BAR.......................................................................................... 757

FIGURE 7-108: RESIZABLE BAR CAPABILITY............................................................................. 759

FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 759

FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER............................................................. 760

FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER ................................................................ 761

FIGURE 7-112: ARI CAPABILITY................................................................................................. 762

IGURE 7-113: ARI CAPABILITY HEADER .................................................................................. 763

FIGURE 7-114: ARI CAPABILITY REGISTER ................................................................................ 763

IGURE 7-115: ARI CONTROL REGISTER .................................................................................... 764

IGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 765

FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER ............................................................... 765

FIGURE 7-118: DPA CAPABILITY REGISTER ............................................................................... 766

IGURE 7-119: DPA LATENCY INDICATOR REGISTER................................................................. 767

FIGURE 7-120: DPA STATUS REGISTER ...................................................................................... 767

IGURE 7-121: DPA CONTROL REGISTER ................................................................................... 768

FIGURE 7-122: DPA POWER ALLOCATION ARRAY ..................................................................... 768

FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 769

IGURE 7-124: LTR EXTENDED CAPABILITY HEADER................................................................ 769

FIGURE 7-125: MAX SNOOP LATENCY REGISTER ....................................................................... 770

IGURE 7-126: MAX NO-SNOOP LATENCY REGISTER................................................................. 770

IGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE .......................................................... 771

IGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER............................................ 772

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER............................................................ 772

FIGURE 7-130: TPH REQUESTER CONTROL REGISTER................................................................ 774

FIGURE 7-131: TPH ST TABLE ................................................................................................... 775

IGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE........................ 776

IGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER.............................. 776

FIGURE 7-134: LINK CONTROL 3 REGISTER ................................................................................ 777

FIGURE 7-135: LANE ERROR STATUS REGISTER ......................................................................... 778

FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER ......................................................... 778

IGURE 7-137: LANE ((MAXIMUM LINK WIDTH – 1):0) EQUALIZATION CONTROL REGISTER .... 779

IGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER

COMMUNICATION MODELS.................................................................................................. 784

FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND

CONGESTION........................................................................................................................ 785

IGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS

............................................................................................................................................. 790

FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF 0 ............................... 810

FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 819

FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK................................ 827

FIGURE G-2: PMUX LINK .......................................................................................................... 828

FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS ...................................................... 829

FIGURE G-4: PMUX PACKET...................................................................................................... 836

FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING)....................................... 837

FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING)................................ 839

FIGURE G-7: PMUX EXTENDED CAPABILITY ............................................................................. 843

FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER............................................................... 843

FIGURE G-9: PMUX CAPABILITY REGISTER............................................................................... 844

FIGURE G-10: PMUX CONTROL REGISTER................................................................................. 846

FIGURE G-11: PMUX STATUS REGISTER.................................................................................... 847

FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY....................................................................... 850

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

Tables

TABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES........................................... 54

ABLE 2-2: FMT[2:0] FIELD VALUES ............................................................................................ 59

TABLE 2-3: FMT[2:0] AND TYPE[4:0] FIELD ENCODINGS.............................................................. 60

ABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 61

ABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 66

TABLE 2-6: ADDRESS FIELD MAPPING.......................................................................................... 66

TABLE 2-7: HEADER FIELD LOCATIONS FOR NON-ARI ID ROUTING............................................. 68

TABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING..................................................... 68

ABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE................................................... 70

ABLE 2-10: ORDERING ATTRIBUTES ........................................................................................... 75

TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 76

TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS...................................................................... 76

TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS................................................. 77

TABLE 2-14: TPH TLP PREFIX BIT MAPPING ............................................................................... 81

TABLE 2-15: LOCATION OF PH[1:0] IN TLP HEADER.................................................................... 82

TABLE 2-16: PROCESSING HINT ENCODING .................................................................................. 82

TABLE 2-17: LOCATION OF ST[7:0] IN TLP HEADERS .................................................................. 83

TABLE 2-18: MESSAGE ROUTING.................................................................................................. 85

TABLE 2-19: INTX MECHANISM MESSAGES ................................................................................. 86

TABLE 2-20: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 88

TABLE 2-21: POWER MANAGEMENT MESSAGES........................................................................... 90

TABLE 2-22: ERROR SIGNALING MESSAGES ................................................................................. 91

TABLE 2-23: UNLOCK MESSAGE................................................................................................... 92

TABLE 2-24: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 92

TABLE 2-25: VENDOR_DEFINED MESSAGES................................................................................. 93

TABLE 2-26: IGNORED MESSAGES ................................................................................................ 95

TABLE 2-27: LTR MESSAGE ......................................................................................................... 95

TABLE 2-28: OBFF MESSAGE....................................................................................................... 96

ABLE 2-29: COMPLETION STATUS FIELD VALUES....................................................................... 98

TABLE 2-30: LOCAL TLP PREFIX TYPES..................................................................................... 101

ABLE 2-31: END-END TLP PREFIX TYPES................................................................................. 102

ABLE 2-32: CALCULATING BYTE COUNT FROM LENGTH AND BYTE ENABLES.......................... 117

TABLE 2-33: CALCULATING LOWER ADDRESS FROM 1

DW BE............................................... 118

TABLE 2-34: ORDERING RULES SUMMARY ................................................................................. 123

ABLE 2-35: TC TO VC MAPPING EXAMPLE .............................................................................. 131

TABLE 2-36: FLOW CONTROL CREDIT TYPES ............................................................................. 135

TABLE 2-37: TLP FLOW CONTROL CREDIT CONSUMPTION ........................................................ 135

ABLE 2-38: MINIMUM INITIAL FLOW CONTROL ADVERTISEMENTS .......................................... 136

TABLE 2-39: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 2.5 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144

TABLE 2-40: UPDATEFC TRANSMISSION LATENCY GUIDELINES FOR 5.0 GT/S MODE OPERATION

LINK WIDTH AND MAX PAYLOAD (SYMBOL TIMES) ...................................................... 144

剩余859页未读，继续阅读

老⑥堂㊣堂主

粉丝: 0
资源: 3

会员权益专享

"PCIe-3.0总线规范：历史版本及修订情况"

评论0

会员权益专享

最新资源

"PCIe-3.0总线规范：历史版本及修订情况"

评论0

PCIe 3.0 规范文档

pcie_3.0协议规范.zip

PCIe规范各版本合集（1.0a、2.0、2.1、3.0、4.0、5.0）

pcie3.0总线规范.pdf

pcie3.0协议规范

pcie3.0规范中文版

pcie 3.0规范中文版

pcie-xxx-02-x-d-th-footprint

pcie3.0 cem pdf

pcie3.0手册中文

pcie3.0接口尺寸

pcie3.0 spec

pcie3.0信号完整性测试

pcie3.0 specification

pcie1.0可以刷成3.0吗

pcie3.0要求采样率

pcie1.0 2.0 3.0

PCIE3.0协议中文版

pci express3.0协议规范百度文档

pcie_3_0_phy_test_spec_ve

会员权益专享

最新资源