高性能电荷泵：优化静态与动态匹配特性

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本文介绍了一种高性能电荷泵（Charge Pump，CP），其核心特征在于显著提升了静态和动态匹配性能。设计者Haibin Shao、Ke Lin等人，来自北京大学深圳研究生院集成微系统实验室，通过采用伪级联结构和 bulk-biasing 技术，实现了宽电压范围内的高等效输出阻抗，确保了在各种工作条件下的稳定性和效率。首先，伪级联结构有助于降低噪声和失真，通过分段处理输入信号，提高了输出电流的精度和一致性。这种结构减少了静态失配的影响，使得电荷泵在不同工作条件下都能保持较高的精度。Bulk-biasing技术则进一步优化了电源管理，通过调整基区偏置来增强输出电压的控制能力，增强了动态响应速度。作者对电荷泵的开关机制进行了深入分析，为了减少电流切换时的耦合效应，他们在电路中加入了MOS管，有效地降低了导通时间，从而提高了整体的能源效率。同时，额外添加了一个放电路径，加快了关断过程，确保了快速的动态响应特性。该设计在SMIC 130纳米CMOS工艺平台上得以实现。模拟结果显示，即使在供应电压、温度等参数变化下，电荷泵的最大静态失配仅达到0.37%，显示出极高的静态匹配性能。此外，输出锁相环路（VCO）控制电压的峰峰值仅为1.97毫伏，表明了出色的动态稳定性。在输出信号中，参考噪声级别达到了惊人的-73.1分贝，这是对低噪声设计的有效证明。这项研究不仅提升了电荷泵的基本性能，还兼顾了低失真和高速度的需求，对于在各种应用中，如数据转换、信号处理和无线通信等领域中的高性能电子系统具有重要意义。这种高性能电荷泵的设计方法和技术对于推动现代电子设备的小型化、高效能以及信号处理质量的提升具有深远影响。

A High-Performance Charge Pump with Improved Static and

Dynamic Matching Characteristic

Haibin Shao, Ke Lin, Bo Wang*, Chen Chen, Fang Gao, Feng Huang, Xin’an Wang

The Key Laboratory of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, China

* Email: wangbo@ pkusz.edu.cn

Abstract

A high-performance Charge Pump (CP) is introduced in

this paper with both perfect static and dynamic matching

properties. Pseudo-cascode structure and bulk-biasing

technique are adopted to obtain a high equivalent output

impedance over a wide voltage range as well as a fast

transient behavior. Besides, by analyzing turn-on and

turn-off mechanisms, a MOS capacitor is inserted to

weaken the coupling from current switch to reduce the

conduction time and an extra discharging path is added

to accelerate the turn-off speed. A prototype is

implemented in SMIC 130nm CMOS process. The

simulation results show that the maximum static

mismatch is only 0.37% and the largest ripple on VCO

control voltage is 1.97mV over process, temperature and

supply voltage variable. The amount of reference spur is

-73.1dBc in the PLL output signal while the

conventional one’s level is -52dBc.

1. Introduction

A charge pump sinks or sources current for a limited

period of time. The charge pump combined with the PFD

acts like an integrator and provides an open-loop pole to

form a type-II PLL system which can achieve zero static

phase error. But non-ideal effects such as leakage current,

sink & source current mismatch, dynamic mismatch and

etc. will lead to phase offset and reference spur. In this

work, we consider all these issues and then give out the

equations of phase offset and spurs which are listed in

Section 2. Some techniques are adopted like

pseudo-cascode structure, bulk biasing and etc. to give

an improved static and dynamic matching characteristic.

The proposed charge pump is demonstrated in Section 3,

and its post-simulation results are described in Section 4.

2. Non-Ideal effects of Charge Pump

For practical PFD/CP circuit, several imperfections

always exit and it will lead to static phase error and high

ripple on the control voltage even when the loop is

locked. The ripple will be modulated to the PLL output

and cause the reference spur. In frequency synthesis, the

spur caused by CP is dominant source.

The leakage current, sink & source current mismatch and

switch delay difference are the major considerations.

Other than these static behaviors above, the transient

dynamic mismatch will also degrade the spur feature

which is always overlooked.

By taking all these into account, the phase error and

reference spur can be approximated by following

equations [1, 2]:

leakage mismatch switch

leakage

on d

CP ref CP ref CP ref

ti t q

ITITIT

II I I

 

§·

''' '



¨¸

©¹

(1)

2(2)

20log

(2 ) (2 )

20log

leakage

CP ref CP

spur

ref

on d on

ref ref ref CP ref

ref

ITI

tt t q

TT TIT

½

ªº



°°

«»

°°

«»

®¾

«»

'' ' '

°°



«»

°°

«»

¬¼

¯¿



(2)

In the equation,

is the CP current,

ref

and

ref

is the

period and frequency of reference clock,

is the loop

band width of PLL,

is the pole of the low-pass filter

and N is the divider ratio.

leakage

refer to

leakage current, turn-on time of PFD which is used to

avoid the dead-zone, current mismatch and switch delay

difference respectively.

is the dynamic unequal

charge and can be calculated by integration.

In the CPPLL application, the phase error due to the

undesirable effects is usually negligible but the reference

spur is possibly substantial. From equation (2), some

methods to decrease spur can be proposed.

a) Halve the divider ratio and the loop band width can

both lead to 3dB improvement of reference spur;

b) A minimum turn-on time is important to reduce

in-band noise contribution for it appears in three

formulas. But it’s limited by the dead-zone time;

c) Reduce the mismatch and the leakage current, so a

large CP current is always a nice choose as long as

the power match the requirements;

d) Reduce the switch delay mismatch which can be

implemented by adding extra delay cells to get a

better feature;

e) Reduce the dynamic charge mismatch. The current

on and off time, the clock feed-through, the charge

sharing etc. should be considered carefully.

Above all the approaches, some belong to system level

and the others are circuit level. The working frequency

band, divider ratio and loop band width are decided by

the over-all PLL system and are listed in Table 1. This

article will focus on the circuit level to optimize spur

property.

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