CS8900 ISA以太网控制器：集成设计与特性概览

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CS8900是一款专为ISA架构个人计算机设计的低成本以太网控制器硬件板，其主要特点包括： 1. 单芯片设计：这款控制器集成了IEEE 802.3标准的以太网功能，通过直接连接到ISA总线，简化了系统集成，并降低了总体成本。 2. 高效的包页传输模式 (Packet Page TMA): 它采用了高效的I/O和内存空间操作模式，作为DMA从属设备，能够在不占用大量CPU资源的情况下高效处理数据包。 3. 全双工功能：支持数据在发送和接收通道上同时进行，提高了网络通信的带宽利用率和稳定性。 4. 内置RAM缓冲区：为了减少外部存储器访问，控制器内置了用于存储待发送和接收帧的RAM，进一步提升了性能。 5. 多种端口选项：配备10BASE-T端口，具备模拟滤波器，能自动检测和纠正极性问题；同时提供AUI端口，支持10BASE2、10BASE5和10BASE-F不同的以太网物理层标准。 6. 可编程传输特性：具备自动重传碰撞机制，以及自动填充和CRC（循环冗余校验）生成功能，增强数据传输的可靠性。 7. 可编程接收功能：采用流传输TM技术，降低CPU负载；可以自动切换到DMA或内部RAM，实现数据处理的灵活性；并提供早期中断，便于预处理帧；具有自动拒绝错误数据包的功能，确保数据准确性。 8. EEPROM支持：通过跳线设置，用户可以方便地进行配置，简化了初始设置过程。 9. 启动 PROM 支持：对于无盘系统，CS8900提供了Boot PROM功能，简化了系统的引导流程。 10. 边界扫描和环回测试：用于诊断和测试网络连接的实用工具，确保硬件工作的正常性。 11. LED驱动器：用于显示链路状态和局域网活动，帮助用户直观了解网络工作状况。 12. 节能模式：支持待机和休眠模式，有助于节省电力，延长设备寿命。 CS8900以其高度集成、低功耗和丰富的功能特性，成为ISA架构个人计算机中理想的以太网控制器解决方案，尤其适合对性价比要求较高的工业级应用场合。

Upon exit, there is a chip-wide reset (see Section

3.7 for more information about SW Suspend).

3.3.2 Allowing Time for Reset Operation

After a reset, the CS8900 goes through a self

configuration. This includes calibrating on-chip

analog circuitry, and reading EEPROM for valid-

ity and configuration. Time required for the reset

calibration is typically 10 ms. Software drivers

should not access registers internal to the

CS8900 during this time. When calibration is

done, bit INITD in the Self Status Register (reg-

ister 16) is set indicating that initialization is

complete, and the SIBUSY bit in the same regis-

ter is cleared indicating the EEPROM is no

longer being read or programmed.

3.3.3 Bus Reset Considerations

The CS8900 reads 3000h from IObase+0Ah af-

ter the reset, until the software writes a non-zero

value at IObase+0Ah. The 3000h address can be

used as part of the CS8900 signature when the

system scans for the CS8900. See Section 4.10,

I/O Space Operation.

After a reset, the ISA bus outputs INTRx and

DMARQx are tri-stated, thus avoiding any inter-

rupt or DMA channel conflicts on the ISA bus at

power-up time.

Initialization

After each reset (except EEPROM Reset), the

CS8900 checks the sense of the EEDataIn pin to

see if an external EEPROM is present. If EEDI

is high, an EEPROM is present and the CS8900

automatically loads the configuration data stored

in the EEPROM into its internal registers (see

next section). If EEDI is low, an EEPROM is not

present and the CS8900 comes out of reset with

the default configuration shown in Table 3.3.

A low-cost serial EEPROM can be used to store

configuration information that is automatically

PacketPage

Address

Contents

Description

0020h 0300h I/O Base Address*

0022h XXXX XXXX

XXXX X100

Interrupt Number

0024h XXXX XXXX

XXXX XX11

DMA Channel

0026h 0000h DMA Start of Frame

Offset

0028h X000h DMA Frame Count

002Ah 0000h DMA Byte Count

002Ch XXX0 0000h Memory Base Address

0030h XXX0 0000h Boot PROM Base

Address

0034h XXX0 0000h Boot PROM Address

Mask

0102h 0003h Register 3 - RxCFG

0104h 0005h Register 5 - RxCTL

0106h 0007h Register 7 - TxCFG

0108h 0009h Register 9 - TxCMD

010Ah 000Bh Register B - BufCFG

010Ch Undefined Reserved

010Eh Undefined Reserved

0110h Undefined Reserved

0112h 0013h Register 13 - LineCTL

0114h 0015h Register 15 - SelfCTL

0116h 0017h Register 17 - BusCTL

0118h 0019h Register 19 - TestCTL

* I/O base address is unaffected by Software

Suspend mode.

Table 3.3. Default Configuration

EEPROM Type Size (16-bit words)

’C46 (non-sequential) 64

’CS46 (sequential) 64

’C56 (non-sequential) 128

’CS56 (sequential) 128

’C66 (non-sequential) 256

’CS66 (sequential) 256

Table 3.4. Supported EEPROM Types

CS8900

16 DS150PP2

loaded into the CS8900 after each reset (except

EEPROM reset). The use of an EEPROM is op-

tional and is not required for all applications

(e.g. motherboard designs).

The CS8900 operates with any of six standard

EEPROM’s shown in Table 3.4.

3.4 Configuration with EEPROM

EEPROM Interface

The interface to the EEPROM consists of the

four signals shown in Table 3.5.

EEPROM Memory Organization

If an EEPROM is used to store initial configura-

tion information for the CS8900, the EEPROM

is organized in one or more blocks of 16-bit

words. The first block in EEPROM, referred to

as the Configuration Block, is used to configure

the CS8900 after reset. An example of a typical

Configuration Block is shown in Table 3.6. Ad-

ditional blocks containing user data may be

stored in the EEPROM. However, the Configura-

tion Block must always start at address 00h and

be stored in contiguous memory locations.

Reset Configuration Block

The first block in EEPROM, referred to as the

Reset Configuration Block, is used to automat-

ically program the CS8900 with an initial

configuration after a reset. Additional user data

may also be stored in the EEPROM if space is

available. The additional data are stored as 16-bit

words and can occupy any EEPROM address

space beginning immediately after the end of the

Reset Configuration Block up to address 7Fh,

depending on EEPROM size. This additional

data can only be accessed through software con-

trol (refer to Section 3.5 for more information on

accessing the EEPROM). Address space 80h to

AFh is reserved.

Reset Configuration Block Structure: The Reset

Configuration Block is a block of contiguous 16-

bit words starting at EEPROM address 00h. It

can be divided into three logical sections: a

header, one of more groups of configuration data

words, and a checksum value. All of the words

in the Reset Configuration Block are read se-

quentially by the CS8900 after each reset,

starting with the header and ending with the

checksum. Each group of configuration data is

used to program a PacketPage register (or set of

PacketPage registers in some cases) with an in-

itial non-default value.

Reset Configuration Block Header: The header

(first word of the block located at EEPROM ad-

dress 00h) specifies the type of EEPROM used,

whether or not a Reset Configuration block is

present, and if so, how many bytes of configura-

tion data are stored in the Reset Configuration

Block.

Determining the EEPROM Type: The LSB of

the high byte of the header indicates the type of

EEPROM attached: sequential or non-sequential.

An LSB of 0 (XXXX-XXX0) indicates a se-

quential EEPROM. An LSB of 1

(XXXX-XXX1) indicates a non-sequential

EEPROM. The CS8900 works equally well with

CS8900 Pin

(Pin #)

CS8900 Function EEPROM

EECS

(Pin 3)

EEPROM Chip

Select

Chip Select

EESK

(Pin 4)

1 MHz EEPROM Serial

Clock output

Clock

EEDO

(Pin 5)

EEPROM Data Out

(data to EEPROM)

Data In

EEDI

(Pin 6)

EEPROM Data In (data

from EEPROM)

Data Out

Table 3.5 EEPROM Interface

CS8900

DS150PP2 17

either type of EEPROM. The CS8900 will auto-

matically generate sequential addresses while

reading the Reset Configuration Block if a non-

sequential EEPROM is used.

Checking EEPROM for presence of Reset Con-

figuration Block: The read-out of either a binary

101X-XXX0 or 101X-XXX1 (X = do not care)

from the high byte of the header indicates the

presence of configuration data. Any other read-

out value terminates initialization from the

EEPROM. If an EEPROM is attached but not

used for configuration, Crystal recommends that

the high byte of the first word be programmed

with 00h in order to ensure that the CS8900 will

Word Address Value Description

FIRST WORD in DATA BLOCK

00h A120h Configuration Block Header.

The high byte, A1h, indicates a ’C46 EEPROM is attached. The Link Byte, 20h, indicates

the number of bytes to be used in this block of configuration data.

FIRST GROUP of WORDS

01h 2020h Group Header for first group of words.

Three words to be loaded, beginning at 0020h in PacketPage memory.

02h 0300h I/O Base Address

03h 0003h Interrupt Number

04h 0001h DMA Channel Number

SECOND GROUP of WORDS

05h 502Ch Group Header for second group of words.

Six words to be loaded, beginning at 002Ch in PacketPage memory.

06h E000h Memory Base Address - low word

07h 000Fh Memory Base Address - high word

08h 0000h Boot PROM Base Address - low word

09h 000Dh Boot PROM Base Address - high word

0Ah C000h Boot PROM Address Mask - low word

0Bh 000Fh Boot PROM Address Mask high word

THIRD GROUP of WORDS

0Ch 2158h Group Header for third group of words.

Three words to be loaded, beginning at 0158h in PacketPage memory.

0Dh 0010h Individual Address - IA bits [39-32], bits [47-40]

0Eh 0000h Individual Address - IA bits [23-16], bits [31-24]

0Fh 0000h Individual Address - IA bits [7-0], bits [15-8]

CHECKSUM Value

10h 2800h The high byte, 28h, is the Checksum Value. In this example, the checksum

includes word addresses 00h through 0Fh. The hexadecimal sum of the bytes

is D7h, resulting in a 2’s complement of 28h. The low byte, 00h, provides a

pad to the word boundary.

*FFFFh is a special code indicating that there are no more words in the EEPROM.

Table 3.6. EEPROM Configuration Block Example

CS8900

18 DS150PP2

not attempt to read configuration data from the

EEPROM.

Determining Number of Bytes in the Reset

Configuration Block: The low byte of the Reset

Configuration Block header is known as the link

byte. The value of the Link Byte represents the

number of bytes of configuration data in the Re-

set Configuration Block. The two bytes used for

the header are excluded when calculating the

Link Byte value.

For example, a Reset Configuration Block

header of A104h indicates a non-sequential

EEPROM programmed with a Reset Configura-

tion Block containing 4 bytes of configuration

data. This Reset Configuration Block occupies 6

bytes (3 words) of EEPROM space (2 bytes for

the header and 4 bytes of configuration data).

Groups of Configuration Data

Configuration data are arranged as groups of

words. Each group contains one or more words

of data that are to be loaded into PacketPage reg-

isters. The first word of each group is referred to

as the Group Header. The Group Header indi-

cates the number of words in the group and the

address of the PacketPage register into which the

first data word in the group is to be loaded. Any

remaining words in the group are stored in suc-

cessive PacketPage registers.

Group Header: Bits F through C of the Group

Header specify the number of words in each

group that are to be transferred to PacketPage

registers (see Figure 3.1). This value is two less

than the total number of words in the group, in-

cluding the Group Header. For example, if bits F

through C contain 0001, there are three words in

the group (a Group Header and two words of

configuration data).

Bits 8 through 0 of the Group Header specify a

9-bit PacketPage Address. This address defines

the PacketPage register that will be loaded with

the first word of configuration data from the

group. Bits B though 9 of the Group Header are

forced to 0, restricting the destination address

range to the first 512 bytes of PacketPage mem-

ory. Figure 3.1 shows the format of the Group

header.

Reset Configuration Block Checksum

A checksum is stored in the high byte position

of the word immediately following the last group

of data in the Reset Configuration Block. (The

EEPROM address of the checksum value can be

determined by dividing the value stored in the

Link Byte by two). The checksum value is the

2’s complement of the 8-bit sum (any carry out

of eighth bit is ignored) of all the bytes in the

Reset Configuration Block, excluding the check-

sum byte. This sum includes the Reset

Configuration Block header at address 00h.

Since the checksum value is calculated as the 2 s

complement of the sum of all the preceding

bytes in the in the Reset Configuration Block, a

total of 0 should result when the checksum value

is added to the sum of the previous bytes.

EEPROM Example

Table 3.6 shows an example of a Reset Configu-

ration Block stored in a C46 EEPROM. Note

that little-endian word ordering is used, i.e., the

10325476

First Word of a Group of Words

BADCFE

Number of Words

in Group

9-bit PacketPage Address

Figure 3.1. Group Header

CS8900

DS150PP2 19

least significant word of a multi-word datum is

located at the lowest address.

EEPROM Read-out

If the EEDI pin is asserted high at the end of

reset, the CS8900 reads the first word of

EEPROM data by:

1. Asserting EECS

2. Clocking out a Read-Register-00h command

on EEDO (EESK provides a 1MHz serial clock

signal)

3. Clocking the data in on EEDI.

If the EEDI pin is low at the end of the reset

signal, the CS8900 does not perform an

EEPROM read-out (uses its default configura-

tion).

Determining EEPROM Size: The CS8900 deter-

mines the size of the EEPROM by checking the

sense of EEDI on the tenth rising edge of EESK.

If EEDI is low, the EEPROM is a ’C46 or

’CS46. If EEDI is high, the EEPROM is a ’C56,

’CS56, ’C66, or ’CS66.

Loading Configuration Data: The CS8900 reads

in the first word from the EEPROM to determine

if configuration data is contained in the

EEPROM. If configuration data is not stored in

the EEPROM, the CS8900 terminates initializa-

tion from EEPROM and operates using its

default configuration (See Table 3.3). If configu-

ration data is stored in EEPROM, the CS8900

automatically loads all configuration data stored

in the Reset Configuration Block into its internal

PacketPage registers.

EEPROM Read-out Completion

Once all the configuration data are transferred to

the appropriate PacketPage registers, the CS8900

performs a checksum calculation to verify the

Reset Configuration Blocks data are valid. If the

resulting total is 0, the read-out is considered

valid. Otherwise, the CS8900 initiates a partial

reset to restore the default configuration.

If the read-out is valid, the EEPROMOK bit

(Register 16, SelfST, bit A) is set. EEPROMOK

is cleared if a checksum error is detected. In this

case, the CS8900 performs a partial reset and is

restored to its default. Once initialization is com-

plete (configuration loaded from EEPROM or

reset to default configuration) the INITD bit is

set (Register 16, SelfST, bit 7).

3.5 Programming the EEPROM

After initialization, the host can access the

EEPROM through the CS8900 by writing one of

seven commands to the EEPROM Command

shows the format of the EEPROM Command

EEPROM Commands

The seven commands used to access the

EEPROM are: Read, Write, Erase, Erase/Write

Enable, Erase/Write Disable, Erase-All, and

Write-All. They are described in Table 3.7.

EEPROM Command Execution

During the execution of a command, the two Op-

code bits, followed by six bits of address (for a

’C46 or ’CS46) or eighth bits of address (for a

’C56, ’CS56, ’C66 or ’CS66), are shifted out of

the CS8900, into the EEPROM. If the command

is a Write, the data in the EEPROM Data register

(PacketPage base + 0042h) follows. If the com-

mand is a Read, the data in the specified

EEPROM location is written into the EEPROM

Data register. If the command is an Erase or

Erase-All, no data is transferred to or from the

EEPROM Data register. Before issuing any com-

mand, the host must wait for the SI-BUSY bit

CS8900

20 DS150PP2

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