ESP32技术参考手册

需积分: 14 84 浏览量更新于2024-07-15 收藏 4.99MB PDF 举报

"ESP32 Technical Reference Manual by Espressif Systems, focusing on application development for IoT and ASIC technologies." ESP32技术参考手册是专为应用开发者设计的，提供了关于如何使用ESP32芯片内存和外围设备的详细且全面的信息。手册不仅涵盖了微控制器的基本操作，还深入解析了各种接口和功能模块，帮助开发者充分理解和利用ESP32的功能。手册内容包括但不限于： 1. **内存管理**：ESP32的内存结构，包括闪存、SRAM以及其他存储区域的使用和配置。 2. **外设接口**：详述了I²C、SPI、UART、I2S、SD/MMC等通信协议控制器的使用方法，以及中断和注册表配置。 - I²C控制器在V1.1版本中新增，提供了I²C通信的完整指南。 - SPI在V1.4版本中引入，支持多种工作模式和数据传输配置。 - UART控制器在V1.4版本中添加，涵盖了串行通信的基础和高级设置。 - I2S在V1.5版本中增加，支持音频数据传输和同步操作。 - SD/MMC主机控制器在V1.6版本中加入，用于连接存储卡进行数据读写。 3. **控制与处理单元**：PID/MPU/MMU章节（V1.2）介绍了微处理器控制、内存保护和内存管理单元的使用。 4. **安全特性**：包括eFuse控制器（V1.3），用于硬件安全功能如密钥存储和固件保护；RSA加速器（V1.3）提升了加密算法的性能；随机数生成器（V1.3）为安全应用提供可靠的随机数据源。 5. **GPIO矩阵与IO复用**：更新了IO_MUX和GPIO矩阵寄存器摘要，使开发者能够灵活配置输入输出引脚。 6. **PWM控制**：LED_PWM寄存器摘要的更新，说明了如何通过PWM驱动LED和其他负载。 7. **其他模块**：如I2C控制器中断和注册表在V1.3版本进行了更新，提供了更精确的控制和调试信息。此外，手册还引用了ESP32的数据表，包含了引脚定义、电气特性及封装信息，这些都是硬件设计和系统集成的重要参考。开发者还可以通过ESP32 Resources获取更多的文档和资源，以获取更全面的支持。这个手册的持续更新反映了ESP32平台的不断发展和完善，确保开发者能够跟上最新的功能和技术。每次版本更新都增加了新的章节或改进了现有内容，以满足不断变化的物联网应用需求。因此，对于任何希望利用ESP32开发物联网产品的工程师来说，这本技术参考手册是必不可少的参考资料。

1. SYSTEM AND MEMORY

The block diagram in Figure 1 illustrates the system structure, and the block diagram in Figure 2 illustrates the

address map structure.

Figure 1: System Structure

Figure 2: System Address Mapping

Espressif Systems 15 ESP32 Technical Reference Manual V1.7

1. SYSTEM AND MEMORY

1.3 Functional Description

1.3.1 Address Mapping

Each of the two Harvard Architecture Xtensa LX6 CPUs has 4 GB (32-bit) address space. Address spaces are

symmetric between the two CPUs.

Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~

0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are

shared by the data and instruction bus.

The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access

the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit

word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned

byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction

bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.

Each CPU can directly access embedded memory through both the data bus and the instruction bus, external

memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1

illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.

Some embedded memories and some external memories can be accessed via the data bus or the instruction

bus. In these cases, the same memory is available to either of the CPUs at two address ranges.

Table 1: Address Mapping

Boundary Address

Bus Type

Low Address High Address

Size Target

0x0000_0000 0x3F3F_FFFF Reserved

Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory

Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory

0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved

Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral

Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory

Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory

Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory

0x40C0_0000 0x4FFF_FFFF 244 MB Reserved

Data Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory

0x5000_2000 0xFFFF_FFFF Reserved

1.3.2 Embedded Memory

The Embedded Memory consists of four segments: internal ROM (448 KB), internal SRAM (520 KB), RTC FAST

memory (8 KB) and RTC SLOW memory (8 KB).

The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB).

The 520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and

Internal SRAM 2 (200 KB).

RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.

Table 2 lists all embedded memories and their address ranges on the data and instruction buses.

Espressif Systems 16 ESP32 Technical Reference Manual V1.7

1. SYSTEM AND MEMORY

Table 2: Embedded Memory Address Mapping

Boundary Address

Bus Type

Low Address High Address

Size Target Comment

Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only

0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -

Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -

0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -

Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA

Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA

Boundary Address

Bus Type

Low Address High Address

Size Target Comment

Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap

Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -

0x4006_0000 0x4006_FFFF 64 KB Reserved -

Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache

Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -

Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -

Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap

Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -

Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only

Boundary Address

Bus Type

Low Address High Address

Size Target Comment

Data Instruc-

tion

0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -

1.3.2.1 Internal ROM 0

The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range

0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.

The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to

access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.

While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF

any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done

on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or

DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU,

respectively.

1.3.2.2 Internal ROM 1

The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~

0x3FF9_FFFF of the data bus.

Espressif Systems 17 ESP32 Technical Reference Manual V1.7

1. SYSTEM AND MEMORY

1.3.2.3 Internal SRAM 0

The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64KB to cache external

memory access. When not used as cache, the first 64KB can be read and written by either CPU at addresses

0x4007_0000 ~ 0x4007_7FFF of the instruction bus. The remaining 128 KB can always be read and written by

either CPU at addresses 0x4007_8000 ~ 0x4007_FFFF of instruction bus.

1.3.2.4 Internal SRAM 1

The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses

0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the

instruction bus.

The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the

data bus. That is to say, address

0x3FFE_0000 and 0x400B_FFFC access the same word

0x3FFE_0004 and 0x400B_FFF8 access the same word

0x3FFE_0008 and 0x400B_FFF4 access the same word

……

0x3FFF_FFF4 and 0x400A_0008 access the same word

0x3FFF_FFF8 and 0x400A_0004 access the same word

0x3FFF_FFFC and 0x400A_0000 access the same word

The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not

reversed between address spaces. For example, address

0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.

0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.

0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.

0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.

0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.

0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.

0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.

0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.

……

0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.

0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.

0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.

0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.

0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.

0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.

0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.

0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.

Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more

information.

Espressif Systems 18 ESP32 Technical Reference Manual V1.7

1. SYSTEM AND MEMORY

1.3.2.5 Internal SRAM 2

The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000

~ 0x3FFD_FFFF on the data bus.

1.3.2.6 DMA

DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.

This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and

an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.

In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.

Table 3: Module with DMA

UART0 UART1 UART2

SPI1 SPI2 SPI3

I2S0 I2S1

SDIO Slave SDMMC

EMAC

BT WIFI

1.3.2.7 RTC FAST Memory

RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of

0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the

instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the

APP_CPU.

The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses

0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not

provide access to RTC FAST Memory or any other memory location.

1.3.2.8 RTC SLOW Memory

RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of

0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.

1.3.3 External Memory

The ESP32 can access external SPI flash and SPI SRAM as external memory. Table 4 provides a list of external

memories that can be accessed by either CPU at a range of addresses on the data and instruction buses. When

a CPU accesses external memory through the Cache and MMU, the cache will map the CPU’s address to an

external physical memory address (in the external memory’s address space), according to the MMU settings. Due

to this address mapping, the ESP32 can address up to 16 MB External Flash and 8 MB External SRAM.

Espressif Systems 19 ESP32 Technical Reference Manual V1.7

剩余355页未读，继续阅读

sky123450

粉丝: 0
资源: 7

ESP32技术参考手册

ESP32数据手册.pdf

ESP32_DEVKIT_V1引脚标注图

esp32_technical_reference_manual_cn.pdf

esp32_technical_reference_manual_cn-1.pdf

esp32-s2_technical_reference_manual_cn.pdf

esp32_manual_cn.zip_-baijiahao_esp32_esp32_manual_cn_living7y7_s

esp32.zip_CORE_esp32_esp_bt.h_firstfwz_ladywxf

ESP32_BLE_Arduino.rar_airplane9g1_arduino esp32 ble_esp32_esp32

esp8266_non_os_sdk_api_reference_cn.pdf

最新资源