Analog Devices的ADSP-BF531 Blackfin处理器技术规格

需积分: 14 147 浏览量更新于2024-07-28 收藏 565KB PDF 举报

"ADSP-BF531SBBC400.pdf 是关于Analog Devices公司的Blackfin系列处理器，特别是ADSP-BF533和ADSP-BF531型号的文档。文档包含了该处理器的主要特性、规格以及可能的知识产权信息。" ADSP-BF533和ADSP-BF531是Analog Devices公司生产的Blackfin系列嵌入式处理器。Blackfin处理器是一种结合了数字信号处理(DSP)和微控制器功能的混合信号处理器，适用于需要高性能计算和控制应用的场合。这些处理器的主要特点包括： 1. **高性能**: ADSP-BF531/ADSP-BF533可以达到高达600MHz的运行频率，提供了强大的处理能力。 2. **多核架构**: 设计有双16位乘积累加器(MACs)，双40位算术逻辑单元(ALUs)以及四个8位视频ALUs，这样的架构增强了数据处理能力，特别是在多媒体和信号处理应用中。 3. **40位移位器**: 提供灵活的数据操作和高效的算法执行。 4. **RISC-like特性**: 采用类似于精简指令集计算机(RISC)的寄存器和指令模型，使得编程更为简便，并且有利于编译器优化。 5. **高级调试与性能监控**: 提供了先进的调试、跟踪和性能监测功能，便于开发人员进行问题定位和性能优化。 6. **电源管理**: 内置的电压调节器支持0.8V到1.2V的核心电压(VDD)，有助于降低功耗。 7. **兼容性**: 支持3.3V和2伏特的I/O电压，适应不同的系统需求。值得注意的是，Analog Devices提供的信息被认为是准确可靠的，但不承担由此使用引起的责任，也不保证不会侵犯第三方的专利或其他权利。此外，规格可能会变更而不事先通知，且没有隐含授予任何Analog Devices专利权的许可。所有的商标和注册商标归各自所有者所有。文档可能还包含了这些处理器的引脚配置、电气特性、接口选项、开发工具信息以及应用示例等内容，帮助开发者和工程师全面理解和利用ADSP-BF533和ADSP-BF531处理器的能力。对于设计高性能、低功耗的嵌入式系统，尤其是涉及图像处理、音频处理和实时控制的应用，这些处理器是一个重要的考虑选项。

Rev. 0 | Page 10 of 56 | March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORT

The ADSP-BF531/2/3 processor provides a full-duplex Univer-

sal Asynchronous Receiver/Transmitter (UART) port, which is

fully compatible with PC-standard UARTs. The UART port

provides a simplified UART interface to other peripherals or

hosts, supporting full-duplex, DMA-supported, asynchronous

transfers of serial data. The UART port includes support for 5 to

8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The

UART port supports two modes of operation:

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f

SCLK

/ 1,048,576) to

SCLK

/16) bits per second.

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8bits).

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA®) Serial Infrared Physi-

cal Layer Link Specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFX)

The ADSP-BF531/2/3 processor has 16 bidirectional, general-

purpose Programmable Flag (PF15–0) pins. Each programma-

ble flag can be individually controlled by manipulation of the

flag control, status and interrupt registers:

• Flag Direction Control Register – Specifies the direction of

each individual PFx pin as input or output.

• Flag Control and Status Registers – The ADSP-BF531/2/3

processor employs a “write one to modify” mechanism that

allows any combination of individual flags to be modified

in a single instruction, without affecting the level of any

other flags. Four control registers are provided. One regis-

ter is written in order to set flag values, one register is

written in order to clear flag values, one register is written

in order to toggle flag values, and one register is written in

order to specify a flag value. Reading the flag status register

allows software to interrogate the sense of the flags.

• Flag Interrupt Mask Registers – The two Flag Interrupt

Mask Registers allow each individual PFx pin to function as

an interrupt to the processor. Similar to the two Flag Con-

trol Registers that are used to set and clear individual flag

values, one Flag Interrupt Mask Register sets bits to enable

interrupt function, and the other Flag Interrupt Mask reg-

ister clears bits to disable interrupt function. PFx pins

defined as inputs can be configured to generate hardware

interrupts, while output PFx pins can be triggered by soft-

ware interrupts.

• Flag Interrupt Sensitivity Registers – The two Flag Inter-

rupt Sensitivity Registers specify whether individual PFx

pins are level- or edge-sensitive and specify—if edge-sensi-

tive—whether just the rising edge or both the rising and

falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects which

edges are significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The processor provides a Parallel Peripheral Interface (PPI) that

can connect directly to parallel A/D and D/A converters, ITU-R

601/656 video encoders and decoders, and other general-pur-

pose peripherals. The PPI consists of a dedicated input clock

pin, up to 3 frame synchronization pins, and up to 16 data pins.

The input clock supports parallel data rates up to half the system

clock rate.

In ITU-R 656 modes, the PPI receives and parses a data stream

of 8-bit or 10-bit data elements. On-chip decode of embedded

preamble control and synchronization information is

supported.

Three distinct ITU-R 656 modes are supported:

• Active Video Only - The PPI does not read in any data

between the End of Active Video (EAV) and Start of Active

Video (SAV) preamble symbols, or any data present during

UART Clock Rate

SCLK

16 UART_Divisor×

----------------------------------------------- -

ADSP-BF531/ADSP-BF532/ADSP-BF533

Rev. 0 | Page 11 of 56 | March 2004

the vertical blanking intervals. In this mode, the control

byte sequences are not stored to memory; they are filtered

by the PPI.

• Vertical Blanking Only - The PPI only transfers Vertical

Blanking Interval (VBI) data, as well as horizontal blanking

information and control byte sequences on VBI lines.

• Entire Field - The entire incoming bitstream is read in

through the PPI. This includes active video, control pream-

ble sequences, and ancillary data that may be embedded in

horizontal and vertical blanking intervals.

Though not explicitly supported, ITU-R 656 output functional-

ity can be achieved by setting up the entire frame structure

(including active video, blanking, and control information) in

memory and streaming the data out the PPI in a frame sync-less

mode. The processor’s 2D DMA features facilitate this transfer

by allowing the static frame buffer (blanking and control codes)

to be placed in memory once, and simply updating the active

video information on a per-frame basis.

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications. The

modes are divided into four main categories, each allowing up

to 16 bits of data transfer per PPI_CLK cycle:

• Data Receive with Internally Generated Frame Syncs

• Data Receive with Externally Generated Frame Syncs

• Data Transmit with Internally Generated Frame Syncs

• Data Transmit with Externally Generated Frame Syncs

These modes support ADC/DAC connections, as well as video

communication with hardware signaling. Many of the modes

support more than one level of frame synchronization. If

desired, a programmable delay can be inserted between asser-

tion of a frame sync and reception/transmission of data.

DYNAMIC POWER MANAGEMENT

The ADSP-BF531/2/3 processor provides five operating modes,

each with a different performance/power profile. In addition,

Dynamic Power Management provides the control functions to

dynamically alter the processor core supply voltage, further

reducing power dissipation. Control of clocking to each of the

ADSP-BF531/2/3 processor peripherals also reduces power con-

sumption. See Table 4 for a summary of the power settings for

each mode.

Full-On Operating Mode—Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and sys-

tem clock (SCLK) run at the input clock (CLKIN) frequency. In

this mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is

entered. DMA access is available to appropriately configured L1

memories.

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

Hibernate Operating Mode—Maximum Static Power

Savings

The Hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all the synchronous peripherals (SCLK). The internal voltage

regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V

DDINT

) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory

contents, register contents, etc.) must be written to a non-vola-

tile storage device prior to removing power if the processor state

is to be preserved. Since V

DDEXT

is still supplied in this mode, all

of the external pins tri-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

have power still applied without drawing unwanted current.

The internal supply regulator can be woken up either by a Real-

Time Clock wakeup or by asserting the RESET

pin.

Sleep Operating Mode—High Dynamic Power Savings

The Sleep mode reduces dynamic power dissipation by dis-

abling the clock to the processor core (CCLK). The PLL and

system clock (SCLK), however, continue to operate in this

mode. Typically an external event or RTC activity will wake up

the processor. When in the Sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL Control register (PLL_CTL). If BYPASS is disabled, the

processor will transition to the Full On mode. If BYPASS is

enabled, the processor will transition to the Active mode.

When in the Sleep mode, system DMA access to L1 memory is

not supported.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The Deep Sleep mode maximizes dynamic power savings by

disabling the clocks to the processor core (CCLK) and to all syn-

chronous peripherals (SCLK). Asynchronous peripherals, such

Table 4. Power Settings

Mode PLL PLL

Bypassed

Core

Clock

(CCLK)

System

Clock

(SCLK)

Core

Power

Full On Enabled No Enabled Enabled On

Active Enabled/

Disabled

Yes Enabled Enabled On

Sleep Enabled Disabled Enabled On

Deep Sleep Disabled Disabled Disabled On

Hibernate Disabled Disabled Disabled Off

Rev. 0 | Page 12 of 56 | March 2004

ADSP-BF531/ADSP-BF532/ADSP-BF533

as the RTC, may still be running but will not be able to access

internal resources or external memory. This powered-down

mode can only be exited by assertion of the reset interrupt

(RESET

) or by an asynchronous interrupt generated by the

RTC. When in Deep Sleep mode, an RTC asynchronous inter-

rupt causes the processor to transition to the Active mode.

Assertion of RESET

while in Deep Sleep mode causes the pro-

cessor to transition to the Full-On mode.

Power Savings

As shown in Table 5, the ADSP-BF531/2/3 processor supports

three different power domains. The use of multiple power

domains maximizes flexibility, while maintaining compliance

with industry standards and conventions. By isolating the inter-

nal logic of the ADSP-BF531/2/3 processor into its own power

domain, separate from the RTC and other I/O, the processor

can take advantage of Dynamic Power Management, without

affecting the RTC or other I/O devices. There are no sequencing

requirements for the various power domains.

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

The Dynamic Power Management feature of the ADSP-

BF531/2/3 processor allows both the processor’s input voltage

DDINT

) and clock frequency (f

CCLK

) to be dynamically

controlled.

The savings in power dissipation can be modeled using the

Power Savings Factor and % Power Savings calculations.

The Power Savings Factor is calculated as:

where the variables in the equations are:

•f

CCLKNOM

is the nominal core clock frequency

•f

CCLKRED

is the reduced core clock frequency

•V

DDINTNOM

is the nominal internal supply voltage

•V

DDINTRED

is the reduced internal supply voltage

•T

NOM

is the duration running at f

CCLKNOM

•T

RED

is the duration running at f

CCLKRED

The percent power savings is calculated as:

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator

that can generate processor core voltage levels 0.85V(-5% /

+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V

supply. Figure 7 shows the typical external components

required to complete the power management system.

The regu-

lator controls the internal logic voltage levels and is

programmable with the Voltage Regulator Control Register

(VR_CTL) in increments of 50 mV. To reduce standby power

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while keeping I/O power

DDEXT

) supplied. While in hibernation, V

DDEXT

can still be

applied, eliminating the need for external buffers. The voltage

regulator can be activated from this power-down state either

through an RTC wakeup or by asserting RESET

, which will then

initiate a boot sequence. The regulator can also be disabled and

bypassed at the user’s discretion.

CLOCK SIGNALS

The ADSP-BF531/2/3 processor can be clocked by an external

crystal, a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Table 5. Power Domains

Power Domain VDD Range

All internal logic, except RTC V

DDINT

RTC internal logic and crystal I/O V

DDRTC

All other I/O V

DDEXT

Power Savings Factor

CCLKRED

CCLKNOM

---------------------

DDINTRED

DDINTNOM

--------------------------





RED

NOM

-------------









See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

Figure 7. Voltage Regulator Circuit

% Power Savings 1 Power Savings Factor–()100%×=

DDEXT

DDINT

OUT

1-0

EXTERNAL COMPONENTS

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

NDS8434

ZHCS1000

100 µF

1µF

10 µH

0.1 µF

NOTE: VR

OUT

1-0SHOULDBETIEDTOGETHEREXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.

100 µF

剩余55页未读，继续阅读

yangshan3476

粉丝: 3
资源: 8

Analog Devices的ADSP-BF531 Blackfin处理器技术规格

ADSP-BF531、ADSP-BF532、ADSP-BF533.pdf

ADSP-BF531.rar_ADSP_ADSP BF531_ADSP-BF_ADSP-BF512_BF533-based vi

ADSP-BF52x：处理器.pdf

ADSP-BF533 BlackfinBooting Process.pdf

Blackfin ADSP-BF532处理器简介.pdf

ADI推出ADSP-BF52x处理器系列.pdf

μC_OS-Ⅱ在ADSP-BF531上的移植.pdf

ADSP-BF561-English.rar_english

ADSP-BF531-BF532-BF533.doc

ADI用于光伏逆变器的ADSP-CM41x处理器.pdf

最新资源