Data Sheet AD9371
Rev. B | Page 9 of 57
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Logic Outputs
Output Voltage
High 1375 mV
Low 1025 mV
Differential 225 mV
Offset 1200 mV
DIGITAL SPECIFICATIONS (CMOS),
GPIO_3P3_x SIGNALS
Logic Inputs
Input Voltage
High Level
VDDA_3P3
× 0.8
VDDA_3P3 V
Low Level 0
VDDA_3P3
× 0.2
V
Input Current
High Level −10 +10 μA
Low Level −10 +10 μA
Logic Outputs
Output Voltage
High Level
VDDA_3P3
× 0.8
V
Low Level
VDDA_3P3
× 0.2
V
Drive Capability 4 mA
1
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation.
3
Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.
4
Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal.
5
Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel.
6
dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.
7
Continuous wave (CW) is a single frequency signal.
8
Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard
clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
9
Signal-to-noise ratio is limited by the baseband quantization noise.
CURRENT AND POWER CONSUMPTION SPECIFICATIONS
Table 2.
Parameter Min Typ Max Unit Test Conditions / Comments
SUPPLY CHARACTERISTICS
VDDA_1P3 Analog Supplies
1
1.267 1.3 1.33 V
VDIG Supply 1.267 1.3 1.33 V
VDDA_1P8 Supply 1.71 1.8 1.89 V
VDD_IF Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
VDDA_3P3 Supply 3.135 3.3 3.465 V
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
1.14 1.3 1.365 V
POSITIVE SUPPLY CURRENT (Rx MODE)
Two Rx channels enabled, Tx upconverter disabled, 100 MHz
Rx BW, 122.88 MSPS data rate
VDDA_1P3 Analog Supplies
1
1055 mA
VDIG Supply 625 mA Rx QEC
2
enabled, QEC
2
engine active
VDD_IF Supply (CMOS and LVDS) 8 mA
VDDA_3P3 Supply 1 mA
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
375 mA
Total Power Dissipation 2.70 W
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