ADAU1452：汽车级数字音频处理器

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"ADAU1452是一款由Analog Devices公司生产的数字音频处理器，适用于汽车应用，具有高度可编程性，能实现增强型声音处理功能。该芯片配备了一个专有的图形化编程工具SigmaStudio，用于定制信号流程。其内部包含一个294.912MHz、32位的ΣDSP核心，工作电压为1.2V，在48kHz采样率下可执行高达6144个SIMD指令。设备还配备了40千字节的参数/数据RAM，可在48kHz时提供最长800毫秒的数字音频延迟池。此外，ADAU1452还支持音频输入/输出和路由功能，具备4个串行接口。" **ADAU1452详细知识** 1. **数字音频处理器**：ADAU1452是一个专门设计用于音频处理的数字信号处理器（DSP），它能够高效地处理音频信号，实现各种复杂的音频算法，如均衡器、混响、噪声消除等。 2. ** SigmaDSP内核**：这款处理器的核心是一个高性能的ΣDSP，运行频率为294.912MHz，采用32位架构，这使其在处理音频信号时具有强大的计算能力。 3. **可编程性**：ADAU1452完全可编程，用户可以根据需求编写和修改代码，实现定制化的音频处理效果。这得益于Analog Devices提供的SigmaStudio软件，它是一个直观的图形化编程环境，使得开发者无需深入底层硬件细节就能设计复杂的信号流。 4. **SIMD指令**：单指令多数据（SIMD）技术允许处理器同时处理多个数据点，显著提高了处理大量并行数据的能力。在48kHz采样率下，每样本可以执行6144个SIMD指令，这在实时音频处理中至关重要。 5. **内存资源**：40千字节的参数/数据RAM提供了足够的空间存储算法参数和中间计算结果，确保了处理器在运行复杂音频程序时的稳定性。 6. **数字音频延迟池**：800毫秒的数字音频延迟池允许对音频信号进行延时处理，这在音频系统设计中非常有用，例如在环绕声系统中调整声音到达各个扬声器的时间。 7. **音频I/O和路由**：ADAU1452支持多种音频输入和输出，通过灵活的路由功能，可以方便地连接到不同的音频源和目的地，如麦克风、音频编解码器、功放等。 8. **汽车行业认证**：作为一款适合汽车应用的芯片，ADAU1452满足了汽车级的性能和可靠性标准，能在严苛的汽车环境中稳定工作。 9. **技术支持**：Analog Devices提供全面的技术支持，用户可以通过其官方网站获取最新的文档、示例代码和解决问题的帮助。 ADAU1452是一款高度集成的数字音频处理器，适用于汽车音响系统、专业音频设备以及需要高质量音频处理的任何其他应用。其强大的处理能力、丰富的内存资源和灵活的I/O配置，使得它成为音频系统设计的理想选择。

ADAU1452 Data Sheet

Rev. A | Page 16 of 176

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND

DVDD

SDATA_OUT3

BCLK_OUT3

LRCLK_OUT3/MP9

SDATA_OUT2

BCLK_OUT2

LRCLK_OUT2/MP8

MP7

MP6

SDATA_OUT1

BCLK_OUT1

LRCLK_OUT1/MP5

SDATA_OUT0

BCLK_OUT0

LRCLK_OUT0/MP4

IOVDD

DGND

ADAU1452

TOP VIEW

DVDD

SDATA_IN3

LRCLK_IN3/MP13

BCLK_IN3

SDATA_IN2

LRCLK_IN2/MP12

BCLK_IN2

THD_P

THD_M

SDATA_IN1

LRCLK_IN1/MP11

BCLK_IN1

SDATA_IN0

LRCLK_IN0/MP10

BCLK_IN0

IOVDD

DGND

IOVDD

VDRIVE

SPDIFIN

PDIFOUT

AGND

AVDD

AUXADC0

AUXADC1

AUXADC2

AUXADC3

AUXADC4

AUXADC5

PGND

PVDD

PLLFILT

DGND

IOVDD

DVDD

XTALIN/MCLK

XTALOUT

CLKOUT

RESET

DGND

SS_M/MP0

MOSI_M/MP1

SCL_M/SCLK_M/MP2

SDA_M/MISO_M/MP3

MISO/SDA

SCLK/SCL

MOSI/ADDR1

SS/ADDR0

SELFBOOT

DVDD

DGND

11486-002

NOTES

1. THE EXPOSED PAD MUST BE GROUNDED BY SOLDERING IT TO A COPPER SQUARE

OF EQUIVALENT SIZE ON THE PCB. IDENTICAL COPPER SQUARES MUST EXIST ON

ALL LAYERS OF THE BOARD, CONNECTED BY VIAS, AND THEY MUST BE CONNECTED

TO A DEDICATED COPPER GROUND LAYER WITHIN THE PCB.

Figure 11. Pin Configuration

Table 20. Pin Function Descriptions

No.

Mnemonic

Internal Pull

Resistor

Description

1 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

2 IOVDD None

Input/Output Supply, 1.8 V – 10% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 1 (DGND).

3 VDRIVE None

PNP Bipolar Junction Transistor-Base Drive Bias Pin for the Digital Supply Regulator. Connect to

the base of an external PNP pass transistor (STD2805 is recommended). If an external supply is

provided directly to DVDD, connect the VDRIVE pin to ground.

4 SPDIFIN None

Input to the Integrated Sony/Philips Digital Interface Format Receiver. Leave this pin disconnected

when not in use. This pin is internally biased to IOVDD/2.

5 SPDIFOUT Configurable

Output from the Integrated Sony/Philips Digital Interface Format Transmitter. Leave this pin

disconnected when not in use.

6 AGND None

Analog Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common

ground plane.

7 AVDD None

Analog (Auxiliary ADC) Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors

to Pin 6 (AGND).

8 AUXADC0 None

Auxiliary ADC Input Channel 0. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

9 AUXADC1 None

Auxiliary ADC Input Channel 1. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

10 AUXADC2 None

Auxiliary ADC Input Channel 2. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

Data Sheet ADAU1452

Rev. A | Page 17 of 176

No. Mnemonic

Internal Pull

Resistor Description

11 AUXADC3 None

Auxiliary ADC Input Channel 3. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

12 AUXADC4 None

Auxiliary ADC Input Channel 4. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

13 AUXADC5 None

Auxiliary ADC Input Channel 5. This pin reads an analog input signal and uses its value in the

DSP program. Leave this pin disconnected when not in use.

14 PGND None

PLL Ground Reference. Tie all DGND, AGND, and PGND pins directly together in a common

ground plane.

15 PVDD None PLL Supply. Must be 3.3 V ± 10%. Bypass this pin with decoupling capacitors to Pin 14 (PGND).

16 PLLFILT None

PLL Filter. The voltage on the PLLFILT pin, which is internally generated, is typically between

1.65 V and 2.10 V.

17 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

18 IOVDD None

Input/Output Supply, 1.8 V – 10% to 3.3 V + 10%. Bypass this pin to Pin 17 (DGND) with

decoupling capacitors.

19 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

20 DVDD None

Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass this pin to Pin 19 (DGND) with decoupling

capacitors.

21 XTALIN/MCLK None

Crystal Oscillator Input (XTALIN)/Master Clock Input to the PLL (MCLK). This pin can be supplied

directly or generated by driving a crystal with the internal crystal oscillator via Pin 22 (XTALOUT).

If a crystal is used, refer to the circuit shown in Figure 14.

22 XTALOUT None

Crystal Oscillator Output for Driving an External Crystal. If a crystal is used, refer to the circuit

shown in Figure 14. Leave this pin disconnected when not in use.

23 CLKOUT Configurable

Master Clock Output. This pin drives a master clock signal to other ICs in the system. CLKOUT

can be configured to output a clock signal with a frequency of 1×, 2×, 4×, or 8× the frequency

of the divided clock signal being input to the PLL. Leave this pin disconnected when not in use.

RESET

Pull-down

Active Low Reset Input. A reset is triggered on a high-to-low edge and exited on a low-to-high

edge. A reset event sets all RAMs and registers to their default values.

25 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

26 SS_M/MP0

Pull-up; nominally

250 kΩ; can be

disabled by a write

to control register

SPI Master/Slave Select Port (SS_M)/Multipurpose, General-Purpose Input/Output (MP0). When

in SPI master mode, this pin acts as the slave select signal to slave devices on the SPI bus. The

pin must go low at the beginning of a master SPI transaction and high at the end of a transaction.

This pin has an internal pull-up resistor that is nominally 250 kΩ. When the SELFBOOT pin is

held high and the RESET

pin has a transition from low to high, Pin 26 sets the communications

protocol for self boot operation. If this pin is left floating, the SPI communications protocol is

used for self boot operation. If this pin has a 10 kΩ pull-down resistor to GND, the I

C communi-

cations protocol is used for self boot operation. When self boot operation is not used and this

pin is not needed as a general-purpose input or output, leave it disconnected.

27 MOSI_M/MP1

Pull-up; can be

disabled by a write

to control register

SPI Master Data Output Port (MOSI_M)/Multipurpose, General-Purpose Input/Output (MP1).

When in SPI master mode, this pin sends data from the SPI master port to slave devices on the

SPI bus. Leave this pin disconnected when not in use.

SCL_M/

SCLK_M/MP2

Pull-up; can be

disabled by a write

to control register

C Master Serial Clock Port (SCL_M)/SPI Master Mode Slave Select (SCLK_M)/Multipurpose,

General-Purpose Input/Output (MP2). When in I

C master mode, this pin functions as an open

collector output and drives a serial clock to slave devices on the I

C bus; use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When in SPI master mode, this pin drives

the clock signal to slave devices on the SPI bus. Leave this pin disconnected when not in use.

SDA_M/

MISO_M/MP3

Pull-up; can be

disabled by a write

to control register

C Master Port Serial Data (SDA_M)/SPI Master Mode Data Input (MISO_M)/Multipurpose,

General-Purpose Input/Output (MP3). When in I

C master mode, this pin functions as a bi-

directional open collector data line between the I

C master port and slave devices on the I

C bus;

use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When in SPI master mode,

this pin receives data from slave devices on the SPI bus. Leave this pin disconnected when not

in use.

ADAU1452 Data Sheet

Rev. A | Page 18 of 176

No. Mnemonic

Internal Pull

Resistor Description

30 MISO/SDA

Pull-up; can be

disabled by a write

to control register

SPI Slave Data Output Port (MISO)/I

C Slave Serial Data Port (SDA). In SPI slave mode, this pin

outputs data to the master device on the SPI bus. In I

C slave mode, this pin functions as a bi-

directional open collector data line between the I

C slave port and the master device on the

C bus; use a 2.0 kΩ pull-up resistor to IOVDD on the line connected to this pin. When this pin

is not in use, connect it to IOVDD with a 10.0 kΩ pull-up resistor.

31 SCLK/SCL

Pull-up; can be

disabled by a write

to control register

SPI Slave Port Serial Clock (SCLK)/I

C Slave Port Serial Clock (SCL). In SPI slave mode, this pin

receives the serial clock signal from the master device on the SPI bus. In I

C slave mode, this pin

receives the serial clock signal from the master device on the I

C bus; use a 2.0 kΩ pull-up

resistor to IOVDD on the line connected to this pin. When this pin is not in use, connect it to

IOVDD with a 10.0 kΩ pull-up resistor.

32 MOSI/ADDR1

Pull-up; can be

disabled by a write

to control register

SPI Slave Port Data Input (MOSI)/I

C Slave Port Address MSB (ADDR1). In SPI slave mode, this pin

receives a data signal from the master device on the SPI bus. In I

C slave mode, this pin acts as

an input and sets the chip address of the I

C slave port, in conjunction with Pin 33 (SS/ADDR0).

33 SS/ADDR0

Pull-up, nominally

250 kΩ; can be

disabled by a write

to control register

SPI Slave Port Slave Select (SS)/I

C Slave Port Address LSB (ADDR0). In SPI slave mode, this pin

receives the slave select signal from the master device on the SPI bus. In I

C slave mode, this pin acts

as an input and sets the chip address of the I

C slave port in conjunction with Pin 32 (MOSI/ADDR1).

34 SELFBOOT Pull-up

Self Boot Select. This pin allows the device to perform a self boot, in which it loads its RAM and

self boot operation the next time there is a rising edge on Pin 24 (RESET

). When this pin is

connected to ground, no self boot operation is initiated. This pin can be connected to IOVDD

or to ground either directly or pulled up or down with a 1.0 kΩ or larger resistor.

35 DVDD None

Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass this pin to Pin 36 (DGND) with decoupling

capacitors.

36 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

37 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

38 IOVDD None

Input/Output Supply, 1.8 V – 10% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 37 (DGND).

LRCLK_OUT0/

MP4

Configurable

Frame Clock, Serial Output Port 0 (LRCLK_OUT0)/Multipurpose, General-Purpose Input/Output

(MP4). This pin is bidirectional, with the direction depending on whether Serial Output Port 0

is set up as a master or slave. Leave this pin disconnected when not in use.

40 BCLK_OUT0 Configurable

Bit Clock, Serial Output Port 0. This pin is bidirectional, with the direction depending on whether

the Serial Output Port 0 is set up as a master or slave. Leave this pin disconnected when not in use.

41 SDATA_OUT0 Configurable

Serial Data Output Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Leave this pin disconnected when not in use.

LRCLK_OUT1/

MP5

Configurable

Frame Clock, Serial Output Port 1 (LRCLK_OUT1)/Multipurpose, General-Purpose Input/Output

(MP5). This pin is bidirectional, with the direction depending on whether Serial Output Port 1

is set up as a master or slave. Leave this pin disconnected when not in use.

43 BCLK_OUT1 Configurable

Bit Clock, Serial Output Port 1. This pin is bidirectional, with the direction depending on whether

Output Serial Port 1 is set up as a master or slave. Leave this pin disconnected when not in use.

44 SDATA_OUT1 Configurable

Serial Data Output Port 1 (Channel 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel,

and 16-channel modes. Leave this pin disconnected when not in use.

45 MP6 Configurable Multipurpose, General-Purpose Input/Output 6. Leave this pin disconnected when not in use.

46 MP7 Configurable Multipurpose, General-Purpose Input/Output 7. Leave this pin disconnected when not in use.

LRCLK_OUT2/

MP8

Configurable

Frame Clock, Serial Output Port 2 (LRCLK_OUT2)/Multipurpose, General-Purpose Input/Output

(MP8). This pin is bidirectional, with the direction depending on whether Serial Output Port 2

is set up as a master or slave. Leave this pin disconnected when not in use.

48 BCLK_OUT2 Configurable

Bit Clock, Serial Output Port 2. This pin is bidirectional, with the direction depending on whether

Serial Output Port 2 is set up as a master or slave. Leave this pin disconnected when not in use.

49 SDATA_OUT2 Configurable

Serial Data Output Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel,

or flexible TDM mode. Leave this pin disconnected when not in use.

LRCLK_OUT3/

MP9

Configurable

Frame Clock, Serial Output Port 3 (LRCLK_OUT3)/Multipurpose, General-Purpose Input/Output

(MP9). This pin is bidirectional, with the direction depending on whether Serial Output Port 3

is set up as a master or slave. Leave this pin disconnected when not in use.

Data Sheet ADAU1452

Rev. A | Page 19 of 176

No. Mnemonic

Internal Pull

Resistor Description

51 BCLK_OUT3 Configurable

Bit Clock, Serial Output Port 3. This pin is bidirectional, with the direction depending on

whether Serial Output Port 3 is set up as a master or slave. Leave this pin disconnected when

not in use.

52 SDATA_OUT3 Configurable

Serial Data Output Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel,

8-channel, and flexible TDM modes. Leave this pin disconnected when not in use.

53 DVDD None

Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass Pin 53 with decoupling capacitors to Pin 54 (DGND).

54 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

55 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

56 IOVDD None

Input/Output Supply, 1.8 V – 10% to 3.3 V + 10%. Bypass this pin with decoupling capacitors to

Pin 55 (DGND).

57 BCLK_IN0 Configurable

Bit Clock, Serial Input Port 0. This pin is bidirectional, with the direction depending on whether

Serial Input Port 0 is set up as a master or slave. Leave this pin disconnected when not in use.

LRCLK_IN0/

MP10

Configurable

Frame Clock, Serial Input Port 0 (LRCLK_IN0)/Multipurpose, General-Purpose Input/Output

(MP10). This pin is bidirectional, with the direction depending on whether Serial Input Port 0 is

set up as a master or slave. Leave this pin disconnected when not in use.

59 SDATA_IN0 Configurable

Serial Data Input Port 0 (Channel 0 to Channel 15). Capable of 2-channel, 4-channel, 8-channel,

or 16-channel mode. When not used, this pin can be left disconnected.

60 BCLK_IN1 Configurable

Bit Clock, Serial Input Port 1. This pin is bidirectional, with the direction depending on whether

the Serial Input Port 1 is set up as a master or slave. Leave this pin disconnected when not in use.

LRCLK_IN1/

MP11

Configurable

Frame Clock, Serial Input Port 1 (LRCLK_IN1)/Multipurpose, General-Purpose Input/Output (MP11).

This pin is bidirectional, with the direction depending on whether the Serial Input Port 1 is set up

as a master or slave. Leave this pin disconnected when not in use.

62 SDATA_IN1 Configurable

Serial Data Input Port 1 (Channels 16 to Channel 31). Capable of 2-channel, 4-channel, 8-channel,

or 16-channel mode. Leave this pin disconnected when not in use.

63 THD_M None

Thermal Diode Negative (−) Input. Connect this pin to the D− pin of an external temperature

sensor IC. Leave this pin disconnected when not in use.

64 THD_P None

Thermal Diode Positive (+) Input. Connect this pin to the D+ pin of an external temperature

sensor IC. Leave this pin disconnected when not in use.

65 BCLK_IN2 Configurable

Bit Clock, Serial Input Port 2. This pin is bidirectional, with the direction depending on whether

the Serial Input Port 2 is set up as a master or slave. Leave this pin disconnected when not in use.

LRCLK_IN2/

MP12

Configurable

Frame Clock, Input Serial Port 2 (LRCLK_IN2)/Multipurpose, General-Purpose Input/Output (MP12).

This pin is bidirectional, with the direction depending on whether Serial Input Port 2 is set up

as a master or slave. Leave this pin disconnected when not in use.

67 SDATA_IN2 Configurable

Serial Data Input Port 2 (Channel 32 to Channel 39). Capable of 2-channel, 4-channel, 8-channel,

or flexible TDM mode. Leave this pin disconnected when not in use.

68 BCLK_IN3 Configurable

Bit Clock, Input Serial Port 3. This pin is bidirectional, with the direction depending on whether

Input Serial Port 3 is set up as a master or slave. Leave this pin disconnected when not in use.

LRCLK_IN3/

MP13

Configurable

Frame Clock, Serial Input Port 3 (LRCLK_IN3)/Multipurpose, General-Purpose Input/Output (MP13).

This pin is bidirectional, with the direction depending on whether Serial Input Port 3 is set up

as a master or slave. Leave this pin disconnected when not in use.

70 SDATA_IN3 Configurable

Serial Data Input Port 3 (Channel 40 to Channel 47). Capable of 2-channel, 4-channel, 8-channel,

or flexible TDM mode. Leave this pin disconnected when not in use.

71 DVDD None

Digital Supply. Must be 1.2 V ± 5%. This pin can be supplied externally or by using the internal

regulator and external pass transistor. Bypass with decoupling capacitors to Pin 72 (DGND).

72 DGND None

Digital and I/O Ground Reference. Tie all DGND, AGND, and PGND pins directly together in

a common ground plane.

EP Exposed Pad None

The exposed pad must be grounded by soldering it to a copper square of equivalent size on

the PCB. Identical copper squares must exist on all layers of the board, connected by vias, and

they must be connected to a dedicated copper ground layer within the PCB. For more detailed

information, see Figure 83 and Figure 84.

ADAU1452 Data Sheet

Rev. A | Page 20 of 176

THEORY OF OPERATION

SYSTEM BLOCK DIAGRAM

PLL

LOOP

FILTER

CRYSTAL

RESONATOR

CONTROL CIRCUITRY

(PUSH BUTTONS,

ROTARY

ENCODERS,

POTENTIOMETERS)

SELF BOOT

MEMORY

SYSTEM HOST

CONTROLLER

(MICROCONTROLLER,

MICROPROCESSOR)

S/PDIF OPTICAL

RECEIVER

AUDIO

ADCS

MEMS

MICROPHONES

AUDIO SOURCES

POWER

SUPPLY

TEMPERATURE

SENSOR

CONTROLLER

DIGITAL

AUDIO

SOURCES

S/PDIF OPTICAL

TRANSMITTER

AUDIO

DACS

AUDIO SINKS

DIGITAL

AUDIO

SINKS

LPF

S/PDIF

TRANSMITTER

S/PDIF

RECEIVER

8× 2-CHANNEL

ASYNCHRONOUS

SAMPLE RATE

CONVERTERS

INPUT

CLOCK

DOMAINS

(×4)

OUTPUT

CLOCK

DOMAINS

(×4)

CLOCK

OSCILLATOR

GPIO/

AUX ADC

PLL

C/SPI

SLAVE

REGULATOR

ADAU1452

TEMPERATURE

SENSOR

C/SPI

MASTER

DIGITAL

MIC INPUT

SERIAL DATA

INPUT PORTS

(×4)

SERIAL DATA

OUTPUT PORTS

(×4)

DEJITTER AND

CLOCK GENERATOR

INPUT AUDIO

ROUTING MATRIX

OUTPUT AUDIO

ROUTING MATRIX

11486-013

294.912MHz

PROGRAMMABLE AUDIO

PROCESSING CORE

RAM, ROM, WATCHDOG,

MEMORY PARITY CHECK

Figure 12. System Block Diagram with Example Connections to External Components

OVERVIEW

The ADAU1452 is an enhanced audio processor with 48 channels

of input and output. It includes options for the hardware routing

of audio signals between the various inputs, outputs, SigmaDSP

core, and integrated sample rate converters. The SigmaDSP core

features full 32-bit processing (that is, 64-bit processing in double

precision mode) with an 80-bit arithmetic logic unit (ALU).

By using a quadruple multiply accumulator (MAC) data path,

the ADAU1452 can execute more than 1.2 billion MAC operations

per second, which allows for processing power that far exceeds

the predecessors in the SigmaDSP family of products. The

powerful DSP core can process over 3000 double-precision

biquad filters or 24,000 FIR filter taps per sample at the standard

48 kHz audio sampling rate. Other features, including synchronous

parameter loading for ensuring filter stability and 100% code

efficiency with the SigmaStudio tools, reduce complexity in audio

system development. The SigmaStudio library of audio

processing algorithms allows system designers to compensate for

real-world limitations of speakers, amplifiers, and listening

environments, through speaker equalization, multiband

compression, limiting, and third-party branded algorithms.

The input audio routing matrix and output audio routing matrix

allow the user to multiplex inputs from multiple sources that are

running at various sample rates to or from the SigmaDSP core,

and then to pass them on to the desired hardware outputs. This

drastically reduces the complexity of signal routing and clocking

issues in the audio system. The audio subsystem includes up to

eight stereo asynchronous sample rate converters (ASRCs),

depending on the device model; Sony/Philips Digital Interconnect

Format (S/PDIF) input and output; and serial (I

S) and time

division multiplexing (TDM) I/Os. Any of these inputs can be

routed to the SigmaDSP core or to any of the ASRCs. Similarly,

the output signals can be taken from the SigmaDSP core, any of

the ASRC outputs, the serial inputs, the PDM microphones, or

the S/PDIF receiver. This routing scheme, which can be modified

at any time using control registers, allows for maximum system

flexibility without requiring hardware design changes.

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