UltraFast设计方法学：快速时序收敛指南

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"UG1292 UltraFast时序关闭快速参考指南" UG1292是针对Xilinx FPGA设计的一款详尽且精简的时序收敛快速参考文档，旨在帮助设计者按照UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)中的建议，高效地解决设计中的时序问题，加速设计收敛过程。以下是该文档提供的关键步骤和内容： 1. 初始设计检查(Initial Design Checks) 在实现设计之前，进行以下检查： - **利用率**：确保逻辑资源分配合理，避免过于拥挤或浪费。 - **逻辑级别**：评估门级表示，确保逻辑层次化合理，降低延迟。 - **时序约束**：审查并正确设置时序约束，为后续步骤提供良好的基础。 2. 时序基线设定(Timing Baselining) 在每次实现步骤后，对时序进行审查并处理违规，以协助在布线后完成时序关闭： - 分析实现后的时序报告，识别关键路径上的问题。 - 调整设计或修改约束以改善时序性能。 3. 时序违规解决(Timing Violation Resolution) - **建立时间(setup)违规**：定位触发器输入信号无法在时钟边沿前稳定的原因，可能需要优化路径、调整约束或改变设计结构。 - **保持时间(hold)违规**：查找导致信号在时钟边沿后变化的因素，可能需要使用时钟偏移、增加寄存器或修改时序路径。 4. 快速失败报告(Failfast Report) - 基于Tcl的快速失败报告工具提供设计和约束的关键信息概览，帮助迅速识别和解决常见实施和性能问题。 - 报告比较每个分析指标与典型指导原则，不符合标准的指标标记为“REVIEW”。 - 包含以下部分： - **设计特性**：提供设计的基本信息，如逻辑单元数量、I/O数量等。 - **关键时钟方法论检查**：检查时钟网络是否满足最佳实践，确保时钟质量。 - **保守逻辑级评估**：基于目标最大频率(Fmax)评估逻辑层级，以优化速度性能。通过遵循这些流程，设计师可以有效地提高设计的时序收敛速度，减少设计迭代次数，从而提升设计效率和产品质量。在Xilinx FPGA设计中，理解并应用这些方法对于实现高性能、低功耗的系统至关重要。

This quick reference guide presents the following simplified, step-by-

step flows for quickly closing timing, based on the recommendations in

the UltraFast Design Methodology Guide for the Vivado Design Suite

(UG949):

 Initial Design Checks: Review utilization, logic levels, and timing

constraints before implementing the design.

 Timing Baselining: Review and address timing violations after each

implementation step to help close timing after routing.

 Timing Violation Resolution: Identify the root cause of setup or hold

violations, and resolve the timing violations.

Failfast Report

The Tcl-based failfast report summarizes key information about the

design and constraints, which allows you to quickly identify and address

common implementation and performance issues. By default, the report

analyzes the entire design and outputs a table with each analyzed metric

compared to a typical guideline. Metrics that do not comply with

guidelines are marked as REVIEW. The report includes the following

sections:

 Design characteristics

 Critical clock methodology checks

 Conservative logic-level assessments based on a target Fmax

Starting in the Vivado® tools 2018.1 release, the report_failfast script

is installed by default and can be called as follows:

xilinx::designutils::report_failfast

Starting in the SDx™ tools 2018.2 release, report_failfast is called

during the compilation flow when using xocc –R 1 or xocc –R 2.

For more information on report_failfast, see Failfast Report

Overview (page 10).

Although implementing a design on a Xilinx® device is a fairly automated

task, achieving higher performance and resolving compilation issues due

to timing or routing violations can be a complex and time-consuming

activity. It can be difficult to identify the reason for a failure based on

simple log messages or post-implementation timing reports generated

by the tools. Therefore, it is essential to adopt a step-by-step design

development and compilation methodology, including the review of

intermediate results to ensure the design can proceed to the next

implementation step.

The first step is to make sure all initial design checks are addressed.

Review these checks at the following levels:

 Each kernel made of custom RTL or generated by Vivado HLS

Note: Check that target clock frequency constraints are realistic.

 Each major hierarchy corresponding to a subsystem, such as a

Vivado IP integrator block diagram with several kernels, IP blocks,

and connectivity logic

 Complete design with all major functions and hierarchies, I/O

interfaces, complete clocking circuitry, and physical and timing

constraints

If the design uses floorplanning constraints, such as super logic region

(SLR) assignments or logic assigned to Pblocks, review the estimated

resource utilization for each physical constraint, and make sure that the

utilization guidelines are met. See the default guidelines in the failfast

report. To generate reports, use the following commands:

 report_utilization –pblocks <pblockName>

 report_failfast –pblock <pblockName>

 report_failfast [–slr SLRn | -by_slr]

UG1292 (v2019.1) June 26, 2019

Open the synthesized design checkpoint (DCP) or the post-opt_design DCP

(if available)

Run report_failfast

Review Check Timing section in

report_timing_summary

Run report_methodology

Proceed to design implementation (logic optimization, placement, routing)

Fix methodology checks that impact

timing closure (Fmax)

Create missing clock constraints to

eliminate unconstrained internal

endpoints and avoid timing loops

Review the detailed reports to identify

the design characteristics or

constraints to improve:

● Estimated device and SLR Pblock

resource utilization

● Constraints preventing optimizations

● Control signals and average fanout

● Clock tree and clock domain

crossing constraints

● High logic levels given the target

frequency

Clean report?

Yes

X21574-091818

INTRODUCTION

INITIAL DESIGN CHECKS - DETAILS

INITIAL DESIGN CHECKS FLOW

INITIAL DESIGN CHECKS DETAILS

UltraFast Design Methodology Timing Closure

Quick Reference Guide (UG1292)

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资源: 11

UltraFast设计方法学：快速时序收敛指南

Xilinx UltraFast设计方法学快速时序收敛指南

Xilinx UltraFast嵌入式设计方法与指南

Xilinx UltraFast嵌入式设计方法指南（v2.3）：快速入门与关键要素

ug1292-ultrafast-timing-closure-quick-reference(中文).pdf

ug1231-ultrafast-design-methodology-quick-reference.pdf

中文版 UG1231-ultrafast-design-methodology-quick-reference

ug1228-ultrafast-embedded-design-methodology-guide.pdf

ultrafast-timing-closure.pdf

中文版 UG1046-ultrafast-design-methodology-guide

Xlinx UG1046-ultrafast嵌入式设计方法指南

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