SAR ADC中比较器动态电容非线性校正方法与效果提升

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本文主要探讨了在高分辨率和高速 Successive Approximation Register (SAR) 数模转换器（ADC）中，比较器输入对的动态电容器非线性寄生电容所带来的影响以及相应的校正方法。传统的二进制权重电容阵列结构是SAR ADC设计的核心，然而，这种结构下的电容匹配问题可能会显著降低转换器的性能，如信号与噪声比(SNR)和信躁比(SFDR)。首先，作者分析了动态电容不匹配对SAR ADC性能的具体影响。非线性寄生电容可能导致失调(失调电压)和量化误差的增加，进而影响数字输出的线性和准确性，表现为差动非线性(DNL)和积分非线性(INL)的恶化。这些误差在高分辨率ADC中尤为明显，可能导致信号失真和测量精度下降。针对这一问题，文中提出了两种可行的校正策略。一种是基于补偿网络的设计，通过引入额外的电路元件来抵消或减小非线性电容的影响。另一种则是利用自校准技术，通过对ADC进行周期性的测量和调整，逐步逼近理想状态。这两种方法旨在优化ADC的线性和动态范围，提高其转换精度。为了验证所提出的校正方法的有效性，研究者采用了一款CMOS 40纳米工艺的SAR ADC设计，并进行了深入的后仿真分析。经过校正后的结果表明，该ADC的SFDR和SNDR分别提高了约7分贝和4分贝；在校准后，DNL和INL得到了显著改善，从1.00 LSB和3.81 LSB降至0.67 LSB和0.57 LSB，以及1.46 LSB和0.77 LSB。这说明通过有效的校正策略，SAR ADC的性能得到了显著提升，能够更好地满足高精度测量的需求。本文的研究对于理解和优化SAR ADC的性能至关重要，尤其是在追求更高的转换速度和分辨率时，对比较器动态电容器的非线性寄生电容进行有效校正显得尤为重要。通过理论分析和实践验证，为设计高质量的高性能ADC提供了有价值的技术参考。

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Abstract—This paper proposesa method of correcting the

nonlinear parasitic capacitor of the input pair of comparator in

successive approximations analog-to-digital converters (SAR

ADCs. Thecorrection methodisproposed for the conventional

binary-weighted capacitor array topology usedin most of high

resolution and high speedSAR ADCs. The effects of dynamic

capacitor mismatch are first analyzed and then two feasible

correction schemes are proposed to mitigate the impact of the

nonlinear parasitic capacitor of the comparator. To verify the

effectiveness of the proposed method, we designed a SAR ADCin a

CMOS 40nm process and characterizedthe design byintensive

post-simulations. With the proposed correction schemes,

theSFDR and SNDR of the SAR ADC increase about7 dB and 4

dBrespectively;the DNL and INL after calibration are

improvedfrom 1.00LSB and 3.81LSB to0.67 LSB/0.57LSB and

1.46 LSB/0.77LSBrespectively.

Index Terms—nonlinear parasitic capacitor;high

resolution;successive approximation register;analog-to-digital

converter;dynamic capacitormismatch.

I. INTRODUCTION

ince the development of the first SAR ADC(successive

approximations analog-to-digital converter), ADC

performance has been greatly improved. With CMOS process

scaling down, SAR ADCs are among the most

popularconverters [1] due to itsenergy efficiency. However,

there aremany non-ideal factors limiting the SAR ADC's speed

and dynamic performance, such as capacitor mismatch [2-4],

KT/C noise [5], parasitic capacitors at top plate [6], the

nonlinear parasitic capacitors [7-8], etc..

For high-speed and high-precision SAR ADCs, comparators

based on low-gain and high-bandwidth preamplifiers are often

required. Parasitic capacitors of the input pairs of the

comparatorare MOS transistor capacitors, which are non-linear

capacitors [8]. When shrinking the DAC (digital-to-analog

convertor) unit capacitorto the level of dozens to hundreds of

aFfor high speed, the input parasitic capacitorof the

comparatorshould be considered.In the worst case, the

non-linearityof inputcapacitor will directly affect the

comparator comparison results, so as to affect ADC dynamic

and static performance.Especially, because the comparator

parasitic capacitanceis dependent on the gate voltage, the

varying of the input signal amplitude will dynamically change

This work was supported by theNatural Science Foundation of China under

project 61404022 and 61774028, Science and Technology on Analog

Integrated Circuit Laboratory Foundation under project 0C09YJTJ1603, and

the Fundamental Research Funds for the China Central Universities under

project No. ZYGX2016Z007.

The authors are with the State Key Laboratory of Electronic Thin Films and

Integrated Devices, University of Electronic Science and Technology of

China,Chengdu 610054, China (e-mail: ning_ning@uestc.edu.cn).

the parasitic capacitors’ values.As a result, thehigh harmonic

energy peaks in the output spectrum of the ADC will

increase.Meanwhile, the capacitance of a MOS transistor is

dependent on its bias voltage and the device's threshold

voltageV

th,

of which both are sensitive to the process, voltage

and temperature (PVT) variation.Therefore, it is very

challenging to address the former mentioned issue of

comparator parasitic capacitance for designinga

high-resolution and high-speed SAR ADCs.

1,p

N-1,p

s,p

N,p

. . .

SAR

Logic

ref

1,n

N-1.n

s,n

N,n

. . .

= 2

N-i

, i = 1-N; C

= C

fix,n

fix,p

var,p

var,n

ref

Fig. 1.A conventional N-bit SAR ADC with parasitic capacitors at top plate.

Accumulation

Depletion

max

Inversion

N-type MOS Transistor

Accumulation

Depletion

max

Inversion

1 2 3 4 1234

(a)

(b)

P-type MOS Transistor

min

Fig. 2. The capacitor of N-type and P-type device verse the effective gate

voltage V

, (a) N-type MOS transistor (b) P-type MOS transistor.

In order to solve the issue of nonlinear parasitic capacitorsat

the input of the comparator, the influence of the nonlinear

capacitor on the ADC performance is firstlyinvestigatedina

traditional binary-weighted capacitor array based SAR ADC.It

is found that the nonlinear parasitic capacitorsare most likely to

generate the error results, especially when the

comparator’sdifferential inputsbecome close to each other

around the common-mode voltage. Secondly, two feasible

correction schemes are deduced theoretically based on

mechanism how the parasitic capacitor affects the ADC’s

performance. In the proposed method, the parasitic nonlinear

capacitorat each end of the input pair of comparator is

compensated by an additional MOS transistorcapacitor which

has the opposite device type to the input MOS transistor, so that

the overall effective capacitance is approximatelylinear over

the entire input voltage range. Finally, a 12-bit SAR ADC with

a sampling rate of 100 MHz/s was implemented with the

The Effects ofComparator Dynamic Capacitor

Mismatchin SAR ADC and Correction

Jian Luo,Jing Li,Member IEEE, Ning Ning, MemberIEEE

and YangLiu, MemberIEEE, Qi Yu, MemberIEEE

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