MSP430G2x53 datasheet: Low-power mixed-signal microcontroller with USCI and ultra-fast wake-up features

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本文档详细介绍了TI公司生产的MSP430G2x53和MSP430G2x13这两款混合信号微控制器(Mixed Signal Microcontroller)的特性，对于嵌入式系统和微控制器开发人员具有极高的实用价值。以下是文档中提到的主要知识点： 1. **电源电压范围**：MSP430系列支持低功耗设计，工作电压范围广泛，从1.8V到3.6V，这使得它在各种电池供电应用中非常适用。 2. **通用串行通信接口 (USCI)**：该微控制器内置USCI，提供灵活的串行通信能力，包括UART（通用异步接收/发送器）和可能的IrDA（红外数据自动识别）编码解码器，这对于需要与外部设备进行通信的项目来说是必不可少的。 3. **超低功耗模式**：MSP430G2x53和G2x13具备多种节能模式，如Active模式下仅需230μA电流（1MHz时，2.2V），而在Standby模式下消耗极低，仅为0.5μA，甚至在RAM保留模式下仅有0.1μA，确保了长时间待机时的低功耗运行。 4. **快速唤醒和比较功能**：内置比较器能够在小于1μs的时间内完成模拟信号的比较或斜坡模数转换，这在实时性和响应速度上有着显著的优势。 5. **高性能A/D转换器**：16位RISC架构提供了62.5-ns的A/D转换周期，对于高精度测量应用非常理想。同时，A/D转换器支持10位、200-ksps速率，以及内部参考频率配置，包括高达16MHz的内部时钟。 6. **低功耗辅助组件**：如布朗out检测器和可编程的非常低功耗低频振荡器，有助于在电源不稳定的情况下保持稳定的工作。 7. **方便的编程方式**：支持串行在线编程，无需额外的编程电压，且配备32kHz晶体振荡器，便于固件更新和代码保护。 8. **安全特性**：提供代码保护机制，确保微控制器上的程序代码免受未授权访问。这些特性使得MSP430G2x53和MSP430G2x13成为物联网(IoT)、无线传感器网络(WSN)和电池供电应用的理想选择，特别是那些对功耗敏感且需要高效通信的场景。开发人员在使用这类微控制器时，应详细了解并利用这些特性来优化他们的设计，提高产品的性能和效率。

MSP430G2x53

MSP430G2x13

SLAS735J –APRIL 2011–REVISED MAY 2013

www.ti.com

Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC.

rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

interval timer mode.

OFIE Oscillator fault interrupt enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address 7 6 5 4 3 2 1 0

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault.

PORIFG Power-On Reset interrupt flag. Set on V

power-up.

RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V

power-up.

NMIIFG Set via RST/NMI pin

Address 7 6 5 4 3 2 1 0

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

MSP430G2x53

MSP430G2x13

www.ti.com

SLAS735J –APRIL 2011–REVISED MAY 2013

Memory Organization

Table 8. Memory Organization

MSP430G2253 MSP430G2353 MSP430G2453 MSP430G2553

MSP430G2153

MSP430G2213 MSP430G2313 MSP430G2413 MSP430G2513

Memory Size 1kB 2kB 4kB 8kB 16kB

Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0

Main: code memory Flash 0xFFFF to 0xFC00 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000 0xFFFF to 0xC000

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte 256 Byte

Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h

RAM Size 256 Byte 256 Byte 256 Byte 512 Byte 512 Byte

0x02FF to 0x0200 0x02FF to 0x0200 0x02FF to 0x0200 0x03FF to 0x0200 0x03FF to 0x0200

Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h

8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h

8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to

the MSP430 memory via the BSL is protected by user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's

Guide (SLAU319).

Table 9. BSL Function Pins

20-PIN PW PACKAGE

BSL FUNCTION 28-PIN PACKAGE PW 32-PIN PACKAGE RHB

20-PIN N PACKAGE

Data transmit 3 - P1.1 3 - P1.1 1 - P1.1

Data receive 7 - P1.5 7 - P1.5 5 - P1.5

Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also

called information memory.

• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

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