PCIE系统架构教程：提升工程师效率与市场竞争力

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PCIE系统架构是一个关键的IT领域，专注于PCI Express (PCIe)标准在计算机系统设计中的核心作用。PCIe协议是现代计算机架构中的一种高速接口技术，它在提高数据传输速度、连接性以及系统性能方面扮演着至关重要的角色。这本名为《MindSharc PC!l:xpms System llrchitecture》的教材，由David Churchill、Ravi Budruk、Don Anderson和Tom Shanley等人编辑，旨在通过深入浅出的方式提升读者对PCIe系统架构的理解，从而提高工程师们的生产力和产品上市时间。该教材具有以下特点： 1. **专业知识深度**：作为经典的教材，它详细探讨了PCIe体系结构的各个方面，包括但不限于接口规范、带宽管理、错误检测与恢复机制等，确保学习者能够掌握核心技术。 2. **定制化培训**：MindShare提供的培训方案充分考虑企业的实际需求，提供可扩展的成本效益和灵活的定制选项，确保培训内容贴合公司的特定技术环境。 3. **时间和地点的灵活性**：无论是在传统的课堂环境中，还是在员工的工作站或家中，甚至是多地点同时进行，培训都可以有效地进行，减少了技术人员因培训而耽误工作的时间。 4. **实践导向**：MindShare强调将理论知识应用于实际场景，通过实战训练，使学习者能在真实世界的项目中快速掌握并运用所学知识，提高了技能的实用性。 5. **丰富课程内容**：除了基础概述，还包含高级主题课程，涵盖了从入门到精通的完整学习路径，确保技术团队的知识更新与行业趋势保持同步。 6. **全球化交付**：MindShare的培训服务在全球范围内高效运作，适应不同地区的文化和时区，为跨国公司提供了便捷的解决方案。如果你的公司在技术培训方面的需求没有得到最优化的满足，考虑使用MindShare的专业服务，它们拥有超过25年的经验，能够帮助企业提升技术团队的专业素养，从而推动业务发展和竞争优势的提升。

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Contents

xvii

Immediate Notification of Credits Allocated ....................................................... 311

Maximum Latency Between Update Flow Control DLLPs................................ 311

Calculating Update Frequency Based on Payload Size and Link Width ......... 311

Error Detection Timer — A Pseudo Requirement ...................................................... 312

Chapter 8: Transaction Ordering

Introduction............................................................................................................................. 316

Producer/Consumer Model .................................................................................................. 317

Native PCI Express Ordering Rules ................................................................................... 318

Producer/Consumer Model with Native Devices...................................................... 318

Relaxed Ordering ................................................................................................................... 319

RO Effects on Memory Writes and Messages.............................................................. 319

RO Effects on Memory Read Transactions................................................................... 320

Summary of Strong Ordering Rules.............................................................................. 321

Modified Ordering Rules Improve Performance ............................................................ 322

Strong Ordering Can Result in Transaction Blocking ................................................ 322

The Problem............................................................................................................... 323

The Weakly Ordered Solution ................................................................................ 324

Order Management Accomplished with VC Buffers ................................................. 324

Summary of Modified Ordering Rules......................................................................... 325

Support for PCI Buses and Deadlock Avoidance............................................................ 326

Chapter 9: Interrupts

Two Methods of Interrupt Delivery................................................................................... 330

Message Signaled Interrupts ............................................................................................... 331

The MSI Capability Register Set .................................................................................... 332

Capability ID ............................................................................................................. 332

Pointer To Next New Capability ............................................................................ 333

Message Control Register ........................................................................................ 333

Message Address Register....................................................................................... 335

Message Data Register ............................................................................................. 335

Basics of MSI Configuration........................................................................................... 336

Basics of Generating an MSI Interrupt Request .......................................................... 338

Memory Write Transaction (MSI) .......................................................................... 338

Multiple Messages .................................................................................................... 339

Memory Synchronization When Interrupt Handler Entered.................................... 340

The Problem............................................................................................................... 340

Solving the Problem ................................................................................................. 341

Interrupt Latency ............................................................................................................. 341

MSI Results In ECRC Error ..................................................................................... 341

Some Rules, Recommendations, etc.............................................................................. 341

Contents

xviii

Legacy PCI Interrupt Delivery ............................................................................................ 342

Background — PCI Interrupt Signaling ....................................................................... 342

Device INTx# Pins .................................................................................................... 342

Determining if a Function Uses INTx# Pins ......................................................... 343

Interrupt Routing...................................................................................................... 344

Associating the INTx# Line to an IRQ Number ................................................... 345

INTx# Signaling ........................................................................................................ 345

Interrupt Disable................................................................................................ 346

Interrupt Status .................................................................................................. 346

Virtual INTx Signaling .................................................................................................... 347

Virtual INTx Wire Delivery..................................................................................... 348

Collapsing INTx Signals within a Bridge.............................................................. 349

INTx Message Format .............................................................................................. 351

Devices May Support Both MSI and Legacy Interrupts ................................................ 352

Special Consideration for Base System Peripherals ....................................................... 353

Example System ............................................................................................................... 353

Chapter 10: Error Detection and Handling

Background ............................................................................................................................. 356

Introduction to PCI Express Error Management.............................................................. 356

PCI Express Error Checking Mechanisms.................................................................... 356

Transaction Layer Errors ......................................................................................... 358

Data Link Layer Errors ............................................................................................ 358

Physical Layer Errors ............................................................................................... 358

Error Reporting Mechanisms ......................................................................................... 359

Error Handling Mechanisms.......................................................................................... 360

Sources of PCI Express Errors.............................................................................................. 361

ECRC Generation and Checking ................................................................................... 361

Data Poisoning (Optional) .............................................................................................. 362

TC to VC Mapping Errors............................................................................................... 363

Link Flow Control-Related Errors ................................................................................. 363

Malformed Transaction Layer Packet (TLP)................................................................ 364

Split Transaction Errors .................................................................................................. 365

Unsupported Request .............................................................................................. 365

Completer Abort ....................................................................................................... 366

Unexpected Completion .......................................................................................... 367

Completion Time-out............................................................................................... 367

Error Classifications .............................................................................................................. 368

Correctable Errors............................................................................................................ 369

Uncorrectable Non-Fatal Errors..................................................................................... 369

Uncorrectable Fatal Errors.............................................................................................. 369

How Errors are Reported ...................................................................................................... 370

Contents

xix

Error Messages ................................................................................................................. 370

Completion Status............................................................................................................ 371

Baseline Error Detection and Handling............................................................................. 372

PCI-Compatible Error Reporting Mechanisms ........................................................... 372

Configuration Command and Status Registers................................................... 373

PCI Express Baseline Error Handling ........................................................................... 375

Enabling/Disabling Error Reporting..................................................................... 376

Enabling Error Reporting — Device Control Register................................. 377

Error Status — Device Status Register ........................................................... 378

Link Errors ................................................................................................................. 379

Root’s Response to Error Message ......................................................................... 381

Advanced Error Reporting Mechanisms ........................................................................... 382

ECRC Generation and Checking ................................................................................... 383

Handling Sticky Bits ........................................................................................................ 383

Advanced Correctable Error Handling ........................................................................ 384

Advanced Correctable Error Status ....................................................................... 385

Advanced Correctable Error Reporting ................................................................ 385

Advanced Uncorrectable Error Handling .................................................................... 386

Advanced Uncorrectable Error Status................................................................... 387

Selecting the Severity of Each Uncorrectable Error ............................................. 388

Uncorrectable Error Reporting ............................................................................... 388

Error Logging ...................................................................................................................389

Root Complex Error Tracking and Reporting ............................................................. 390

Root Complex Error Status Registers .................................................................... 390

Advanced Source ID Register ................................................................................. 391

Root Error Command Register ............................................................................... 392

Reporting Errors to the Host System ..................................................................... 392

Summary of Error Logging and Reporting ....................................................................... 392

Part Three: The Physical Layer

Chapter 11: Physical Layer Logic

Physical Layer Overview ...................................................................................................... 397

Disclaimer ......................................................................................................................... 400

Transmit Logic Overview ............................................................................................... 400

Receive Logic Overview ................................................................................................. 402

Physical Layer Link Active State Power Management .............................................. 403

Link Training and Initialization..................................................................................... 403

Transmit Logic Details..........................................................................................................403

Tx Buffer............................................................................................................................ 404

Multiplexer (Mux) and Mux Control Logic ................................................................. 404

Contents

General ....................................................................................................................... 404

Definition of Characters and Symbols................................................................... 405

Byte Striping (Optional).................................................................................................. 408

Packet Format Rules................................................................................................. 411

General Packet Format Rules........................................................................... 411

x1 Packet Format Example ............................................................................... 412

x4 Packet Format Rules..................................................................................... 412

x4 Packet Format Example ............................................................................... 412

x8, x12, x16 or x32 Packet Format Rules......................................................... 413

x8 Packet Format Example ............................................................................... 415

Scrambler........................................................................................................................... 416

Purpose of Scrambling Outbound Transmission................................................. 416

Scrambler Algorithm................................................................................................ 416

Some Scrambler implementation rules:................................................................. 417

Disabling Scrambling ............................................................................................... 418

8b/10b Encoding.............................................................................................................. 419

General ....................................................................................................................... 419

Purpose of Encoding a Character Stream.............................................................. 419

Properties of 10-bit (10b) Symbols.......................................................................... 421

Preparing 8-bit Character Notation........................................................................ 422

Disparity..................................................................................................................... 423

Definition ............................................................................................................ 423

Two Categories of 8-bit Characters................................................................. 423

CRD (Current Running Disparity).................................................................. 423

8b/10b Encoding Procedure ................................................................................... 424

Example Encodings........................................................................................... 424

Example Transmission...................................................................................... 425

The Lookup Tables ................................................................................................... 427

Control Character Encoding ................................................................................... 430

Ordered-Sets.............................................................................................................. 433

General ................................................................................................................ 433

TS1 and TS2 Ordered-Sets................................................................................ 434

SKIP Ordered-Set............................................................................................... 434

Electrical Idle Ordered-Set ............................................................................... 434

FTS Ordered-Set................................................................................................. 434

Parallel-to-Serial Converter (Serializer)........................................................................ 434

Differential Transmit Driver........................................................................................... 435

Transmit (Tx) Clock ......................................................................................................... 435

Other Miscellaneous Transmit Logic Topics ............................................................... 436

Logical Idle Sequence............................................................................................... 436

Inserting Clock Compensation Zones.................................................................... 436

Background ........................................................................................................ 436

Contents

xxi

SKIP Ordered-Set Insertion Rules................................................................... 437

Receive Logic Details ............................................................................................................ 437

Differential Receiver........................................................................................................ 439

Rx Clock Recovery........................................................................................................... 440

General ....................................................................................................................... 440

Achieving Bit Lock ................................................................................................... 440

Losing Bit Lock.......................................................................................................... 441

Regaining Bit Lock.................................................................................................... 441

Serial-to-Parallel converter (Deserializer) .................................................................... 441

Symbol Boundary Sensing (Symbol Lock) ................................................................... 441

Receiver Clock Compensation Logic ............................................................................ 442

Background................................................................................................................ 442

The Elastic Buffer’s Role in the Receiver............................................................... 442

Lane-to-Lane De-Skew .................................................................................................... 444

Not a Problem on a Single-Lane Link.................................................................... 444

Flight Time Varies from Lane-to-Lane .................................................................. 444

If Lane Data Is Not Aligned, Byte Unstriping Wouldn’t Work ......................... 444

TS1/TS2 or FTS Ordered-Sets Used to De-Skew Link ........................................ 444

De-Skew During Link Training, Retraining and L0s Exit................................... 445

Lane-to-Lane De-Skew Capability of Receiver..................................................... 445

8b/10b Decoder................................................................................................................ 446

General ....................................................................................................................... 446

Disparity Calculator ................................................................................................. 446

Code Violation and Disparity Error Detection..................................................... 446

General ................................................................................................................ 446

Code Violations.................................................................................................. 446

Disparity Errors......................................................................................................... 447

De-Scrambler ....................................................................................................................448

Some De-Scrambler Implementation Rules:......................................................... 448

Disabling De-Scrambling......................................................................................... 449

Byte Un-Striping............................................................................................................... 449

Filter and Packet Alignment Check............................................................................... 450

Receive Buffer (Rx Buffer) .............................................................................................. 450

Physical Layer Error Handling ............................................................................................ 450

Response of Data Link Layer to ‘Receiver Error’ Indication.............................. 451

Chapter 12: Electrical Physical Layer

Electrical Physical Layer Overview .................................................................................... 453

High Speed Electrical Signaling ......................................................................................... 455

Clock Requirements......................................................................................................... 456

General ....................................................................................................................... 456

Spread Spectrum Clocking (SSC) ........................................................................... 456

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