VHDL源码实例：探索硬件设计的多样性与威力

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"该资源是一份关于VHDL语言实例的集合，由Ian Elliot of Northumbria University编写，展示了VHDL在描述不同硬件时的多样性和强大功能。实例覆盖了从基本逻辑门描述的简单组合逻辑到微处理器及其相关内存的行为模型等更复杂的系统。所有示例都可以用任何符合IEEE标准的VHDL模拟器进行仿真，并且许多可以使用当前的综合工具进行综合实现。" VHDL（Very High Speed Integrated Circuit Hardware Description Language）是一种用于电子设计自动化（EDA）的高级语言，它允许工程师以文本形式描述数字系统的结构和行为。这份资源提供了多个VHDL描述的实例，旨在帮助学习者理解和掌握VHDL的使用。 1. **组合逻辑**：这部分包括了使用数据流、行为和结构风格描述的异或门，以及各种其他逻辑门的实例，如三输入多数表决器、大小比较器、四输入与非门（74x00系列）以及二进制到七段译码器。这些例子展示了如何使用VHDL创建基本逻辑操作。 2. **计数器**：VHDL可以用于描述计数器，这是数字系统中的常见组件。例如，这些实例可能包含加法计数器、减法计数器或模N计数器，它们展示了如何使用VHDL定义状态转换和计数机制。 3. **移位寄存器**：移位寄存器用于存储和移动数据。这里可能有串行到并行、并行到串行、左移或右移等各种类型的移位寄存器的VHDL实现。 4. **存储器**：这部分可能包含ROM（只读存储器）和RAM（随机访问存储器）的描述，展示如何在VHDL中表示和操作内存单元。 5. **状态机**：状态机是控制逻辑的核心，用于实现顺序逻辑。VHDL可以清晰地定义状态转换图，并将其转换为硬件描述。 6. **寄存器**：寄存器用于临时存储数据。这些实例可能包括D触发器、T触发器和其他类型的寄存器，展示了VHDL在处理时序逻辑中的应用。 7. **系统级设计**：这部分可能涉及更复杂的系统，如微处理器模型和与其相关的内存系统，这展示了VHDL在构建行为模型上的能力。 8. **模数转换器（ADC）和数模转换器（DAC）**：这些是数字系统和模拟世界之间的接口。通过VHDL，可以描述ADC和DAC的内部工作原理和控制逻辑。 9. **算术运算**：VHDL还可以用来描述各种算术操作，如加法、减法、乘法和除法，这对于设计数字信号处理器或计算机的算术逻辑单元至关重要。这份资源是学习和精通VHDL的宝贵材料，涵盖了从基础逻辑门到复杂系统设计的广泛范

Examples of VHDL Descriptions

tin(i) <= '1';

end generate;

t1_size : if i > 0 generate

tin(i) <= q(i-1) and tin(i-1);

end generate;

end v1;

Counter using Multiple Wait Statements

This example shows an inefficient way of describing a counter.

--vhdl model of a 3-state counter illustrating the use

--of the WAIT statement to suspend a process.At each wait

--statement the simulation time is updated one cycle,transferring

--the driver value to the output count.

--This architecture shows that there is no difference between

--WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'

ENTITY cntr3 IS

PORT(clock : IN BIT; count : OUT NATURAL);

END cntr3;

ARCHITECTURE using_wait OF cntr3 IS

BEGIN

PROCESS

BEGIN

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 0;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 1;

--WAIT UNTIL (clock'EVENT AND clock = '1');

WAIT UNTIL clock = '1';

count <= 2;

END PROCESS;

END using_wait;

Counter using a Conversion Function

This counter uses a natural number to hold the count value and converts it into a bit_vector for output. Illustrates the use of a function.

--4-bit binary up counter with asynchronous reset 2/2/93

ENTITY cntr4bit IS

PORT(reset,clock : IN BIT; count : OUT BIT_VECTOR(0 TO 3));

END cntr4bit;

ARCHITECTURE dataflow OF cntr4bit IS

--interface function to generate output bit_vector from

--internal count value.

FUNCTION nat_to_bv(input : NATURAL; highbit : POSITIVE)

RETURN BIT_VECTOR IS

VARIABLE temp : NATURAL := 0;

VARIABLE output : BIT_VECTOR(0 TO highbit);

BEGIN

temp := input;

--check that input fits into (highbit+1) bits

ASSERT (temp <= (2**(highbit + 1) - 1))

REPORT "input no. is out of range" SEVERITY ERROR;

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Examples of VHDL Descriptions

--generate bit values

FOR i IN highbit DOWNTO 0 LOOP

IF temp >= (2**i)

THEN output(i) := '1';

temp := temp - (2**i);

ELSE output(i) := '0';

END IF;

END LOOP;

RETURN output;

END nat_to_bv;

--signal to hold current count value

SIGNAL intcount : NATURAL := 0;

BEGIN

--conditional natural signal assignment models counter

intcount <= 0 WHEN (reset = '1') ELSE

((intcount + 1) MOD 16) WHEN (clock'EVENT AND clock = '1')

ELSE intcount;

--interface function converts natural count to bit_vector count

count <= nat_to_bv(intcount,3);

END;

Quad 2-input Nand

Simple concurrent model of a TTL quad nand gate.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT00 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT00;

architecture VER1 of HCT00 is

begin

Y1 <= A1 nand B1 after 10 ns;

Y2 <= A2 nand B2 after 10 ns;

Y3 <= A3 nand B3 after 10 ns;

Y4 <= A4 nand B4 after 10 ns;

end VER1;

Dual 2-to-4 Decoder

A set of conditional signal assignments model a dual 2-to-4 decoder

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT139 is

port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;

Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);

end HCT139;

architecture VER1 of HCT139 is

begin

Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';

Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';

Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';

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Examples of VHDL Descriptions

Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';

Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';

Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';

end VER1;

Quad D-Type Flip-flop

This example shows how a conditional signal assignment statement could be used to describe sequential logic (it is more common to use a process). The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part

of the language. The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT175 is

port(D : in std_logic_vector(3 downto 0);

Q : out std_logic_vector(3 downto 0);

CLRBAR, CLK : in std_logic);

end HCT175;

architecture VER1 of HCT175 is

begin

Q <= (others => '0') when (CLRBAR = '0')

else D when rising_edge(CLK)

else unaffected;

end VER1;

Octal Bus Transceiver

This example shows the use of the high impedance literal 'Z' provided by std_logic. The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. Ports A and B must be resolved for this model to work correctly (hence std_logic rather than

std_ulogic).

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT245 is

port(A, B : inout std_logic_vector(7 downto 0);

DIR, GBAR : in std_logic);

end HCT245;

architecture VER1 of HCT245 is

begin

A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');

B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');

end VER1;

Quad 2-input OR

--uses 1993 std VHDL

library IEEE;

use IEEE.Std_logic_1164.all;

entity HCT32 is

port(A1, B1, A2, B2, A3, B3, A4, B4 : in std_logic;

Y1, Y2, Y3, Y4 : out std_logic);

end HCT32;

architecture VER1 of HCT32 is

begin

Y1 <= A1 or B1 after 10 ns;

Y2 <= A2 or B2 after 10 ns;

Y3 <= A3 or B3 after 10 ns;

Y4 <= A4 or B4 after 10 ns;

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