XMEGA128 PWM：16位定时器与捕获功能详解

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本文档主要介绍了爱特梅尔AVR XMEGA系列中的128位微控制器，特别是其定时计数器模块的功能和应用。XMEGA器件集成的定时器/计数器具有高级特性，包括： 1. 真正的16位操作：XMEGA的定时器/计数器设计为16位，这意味着它们能够提供精确的计数，支持高分辨率的时间测量和计算。 2. 双缓冲定时周期设置：这种设计允许在不影响当前计数过程的同时，方便地改变定时器的周期设置，提高了灵活性。 3. 多个捕捉/比较通道： - Timer0有4个通道：用于比较或捕捉，可以实现复杂的波形生成和输入信号的捕获。 - Timer1有2个通道：同样具备上述功能，但数量较少，适用于需要较少通道的场合。 4. 32位输入捕获：通过计时器级联，XMEGA可以实现32位的输入捕获，增强了处理复杂信号的能力。 5. 事件计数器：内置事件计数器可用于触发特定事件，例如计数到某个预设值后启动其他功能。 6. 中断和事件处理：提供定时器溢出和错误中断，以及输入捕捉中断，使得系统可以根据计数状态自动执行相应的处理逻辑。 7. 状态定义：文档中定义了关键术语如BOTTOM、MAX和TOP，分别表示计数器达到最低值、最大值和等于序列中最高值的状态。 8. 应用指导：本应用笔记详细介绍了如何利用这些功能进行精确的定时、输入信号捕获和脉宽调制（PWM）控制，这对于开发需要精确时间管理或信号处理的嵌入式系统至关重要。通过学习和理解这些特性，开发人员可以充分利用XMEGA128的定时器/计数器来构建高效、精确的控制电路，提升系统的性能和响应能力。无论是在工业自动化、电机控制还是音频处理等领域，XMEGA128的定时计数器都是不可或缺的组件。

AVR1306

8045A-AVR-02/08

• Timer overflow.

• Timer error (Input capture data lost because input capture buffer is full).

• Compare or capture. Separate interrupts for each channel.

3.4 Period Setting

Each TC module has a period register (PER[H:L]) that controls the TOP value of the

counter (except in frequency generation mode).

The PER[H:L] register is double buffered through the PERBUF[H:L] register. Double

buffered registers are covered in section

3.7.

The PER[H:L] register is automatically initialized to 0xFFFF after a reset.

3.5 Capture or Compare Channels

Each TC module has two or four capture or compare channels. The channels can be

set up for either input capture or compare match. It is not possible to use the same

TC module for both input capture and compare match at the same time. Input capture

can be used to time stamp event, measuring waveform parameters like frequency or

duty cycle. The compare match feature can be used to generate interrupts or events

at certain time points, or for PWM/waveform generation.

The compare or capture channels consist of a set of 16-bit registers named CCx[H:L],

where x indicates the channel. Timer0, with 4 channels, has CCA[H:L], CCB[H:L],

CCC[H:L] and CCD[H:L], while Timer1 has CCA[H:L] and CCB[H:L]. In addition, each

CCx[H:L] register has an associated buffer register CCxBUF[H:L]. Double buffered

registers are covered in detail in section

3.7.

When used for input capture, the value of the PER register determines how input

capture values are interpreted. If bit 15 of PER is set to one, the entire 16 bit counter

value is stored in the capture buffer. If bit 15 of PER is zero, the event polarity is

stored in bit 15 in the capture buffer. This can be used to measure frequency

parameters like duty cycle using only one input pin and one capture channel.

3.6 Event Input Selection

The TC input capture system uses the XMEGA event system to trigger an input

capture. Refer to application note AVR1001 for more information about the XMEGA

event system.

When the TC is used for input capture, all enabled input capture channels must be

associated with an event channel. The EVSEL[3:0] bits of the CTRLD register select

the event channels that are associated with the input capture channels. EVSEL3 must

be 1 to select an event source. EVSEL[2:0] selects between the 8 event channels.

The event channels associated with the different channels cannot be selected

individually.

Table 3-2 shows the mapping between global event channels and input

capture channels when EVSEL3 = 1 and EVSEL[2:0] = N. The “%” is the modulo

operator. Note that when a set of event channels have been selected for the TC, this

does not mean that these event channels are used exclusively by the TC. The TC

simply “listens” to the selected channels and is able to receive events on these event

channels.

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