IEEE Std 1801-2018：低功耗电子系统设计与验证标准

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"IEEE Std 1801-2018是关于低功耗、能源意识的电子系统设计与验证的国际标准，由IEEE计算机学会的设计自动化标准委员会赞助。这个标准详细规定了如何在电子设计中指定功率意图，用于验证设计在特定电源管理架构下的结构和行为，并驱动该电源管理架构的实现。它支持基于IP的设计流程中功率意图规范的增量细化。" IEEE Std 1801-2018标准主要关注以下几个关键知识点： 1. **功率意图(Power Intent)**: 这是标准的核心，定义了一种方法来描述电子设计的功率需求和行为，允许设计者表达电源管理策略，如不同工作模式下的功耗特性。 2. **电源管理架构(Power Management Architecture)**: 标准提供了框架，用于验证设计是否符合预定义的电源管理策略，确保系统在各种运行条件下能有效地管理和消耗电力。 3. **IP重用(IP Reuse)**: 随着集成电路设计的复杂性增加，IP模块的重用变得至关重要。IEEE Std 1801-2018支持在IP复用流程中逐步完善功率意图，确保不同IP模块间的功耗兼容性和一致性。 4. **接口规格(Interface Specification)**: 标准定义了如何清晰地指定设计中不同组件之间的功率交互，这对于确保系统级的功耗优化至关重要。 5. **隔离(Isolation)**: 设计中的某些部分可能需要在特定情况下断电或隔离，以节省能源。标准提供指导，帮助设计者实施这种隔离技术。 6. **电平转换(Level-Shifting)**: 在不同电压域之间进行信号传输时，电平转换是必要的，以防止损坏电路。标准包含关于如何在设计中考虑和实现电平转换的指导。 7. **电源感知设计(Power-Aware Design)**: 该标准推动设计者在整个设计过程中考虑到功耗问题，而不仅仅是作为后端优化的考虑。 8. **电源域(Power Domains)**: 一个电子系统可以被划分为多个电源域，每个域有自己的供电和控制策略。标准阐述了如何定义和管理这些电源域。 9. **功率模式(Power Modes)**: 设备的不同操作模式对应不同的功率消耗。标准提供了描述这些模式的方法，使得设计者能够有效地切换和管理这些模式以达到节能目标。 10. **功率状态(Power States)**: 设计的各个部分可能处于活动、休眠或关闭等不同功率状态。标准指导如何定义和转换这些状态，以适应系统的工作需求。这个标准对于半导体行业、电子设备制造商以及从事低功耗系统设计的工程师来说，是一份重要的参考指南，旨在促进更高效、更节能的电子产品的开发。通过遵循IEEE Std 1801-2018，设计团队可以提高其设计的能效，减少能耗，同时保持系统的性能和可靠性。

IEEE Std 1801-2018

IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

UPF is a concise, power intent specification capability. Power intent can be easily specified over many

elements in the design. A UPF specification can be included with the other deliverables of intellectual

property (IP) blocks and reused along with the other delivered IP. UPF supports various methodologies

through carefully defined semantics, flexibility in specification, and, when needed, defined rational

limitations that facilitate automation in verification and implementation.

1.4 Contents of this standard

The organization of the remainder of this standard is as follows:

 Clause 2 provides references to other applicable standards that are presumed or required for this

standard.

 Clause 3 defines terms and acronyms used throughout the different specifications contained in this

standard.

 Clause 4 describes the basic concepts underlying UPF.

 Clause 5 describes the language basics for UPF and its commands.

 Clause 6 details the syntax and semantics for each UPF power intent command.

 Clause 7 details the syntax and semantics for each UPF power-management cell command.

 Clause 8 defines a reference model for UPF command processing.

 Clause 9 defines simulation semantics for various UPF commands.

 Clause 10 defines the UPF information model.

 Clause 11 defines the UPF information model application programmable interface (API).

 Annex A lists potentially useful additional reference material.

 Annex B lists the predefined value conversion tables (VCTs) for use in power intent specifications.

 Annex C provides sample Tcl procs for retrieving power intent information.

 Annex D summarizes deprecated and legacy commands.

 Annex E provides an overview of UPF tool flows and use model with an illustrative example.

 Annex F provdes a summary of UPF power-management cell command semantics and Liberty

mappings.

 Annex G provides examples of UPF power-management cell modeling.

 Annex H provides an overview of UPF use model for system-level IP power modeling.

 Annex I defines the Switching Activity Interchange Format (SAIF) for representing power-related

activity in a design.

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IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEC 61691-1-1/IEEE Std 1076™, Behavioural languages—Part 1-1: VHDL Language Reference

Manual.

10, 11, 12

IEEE Std 1800™, IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and

Verification Language.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling

Language (UML) Version 1.4.2.

3. Definitions, acronyms, and abbreviations

3.1 Definitions

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online [B1]

should be consulted for terms not defined in Clause 3.

Certain terms in this

standard reflect their corresponding definitions in IEEE Std 1800™ or IEC 61691-1-1/IEEE Std 1076™, or

they are listed in Annex A.

active component: A component that contains one or more input receivers and one or more output drivers

whose values are functions of the inputs, but whose inputs and outputs are not directly connected; or any

hardware description language (HDL) construct(s) that synthesize(s) to an active component.

active control signal: A control signal that is currently presenting the value (level) or transition (edge) that

enables or triggers an active component to operate in a particular manner.

active power state: A power state whose logic expression—or, in certain cases, supply expression—

evaluate to True at a given time.

activity: Any change in the value of a net, regardless of whether that change is propagated to an output.

analog port: A port that is part of a connection that delivers analog signals.

ancestor: Any instance between the current scope in the logic hierarchy and its root scope. When the

current scope is a top-level module, it does not have any ancestors. See also: descendant.

anonymous object: An object that is not named in the context of Unified Power Format (UPF).

Implementations may assign a legal name, but such names are not visible in the UPF context.

IEC publications are available from the International Electrotechnical Commission (http://www.iec.ch) and the American National

Standards Institute (http://www.ansi.org/).

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

The IEEE standards or products referred to in this clause are trademarks of The Institute of Electrical and Electronics Engineers,

Incorporated.

The numbers in brackets correspond to those of the bibliography in Annex A.

IEEE Standards Dictionary Online subscription is available at:

http://www.ieee.org/portal/innovate/products/standard/standards_dictionary.html.

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IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

available in a domain: A supply that can be used by implementation tools to power cells that they insert in

the extent of the domain.

balloon latch: A retention element style in which a register’s value is saved to a dedicated latch at power-

down and the latch value is restored to the register at power-up.

boundary instance: An instance that has no parent or whose parent is in a different power domain.

child domain (of a HighConn port on the lower boundary of a power domain): The power domain

whose upper boundary contains the corresponding LowConn of the HighConn port.

coarse grain switch: A power switch that is used to generate switched supply for a group of library cells.

This is identified using the attribute

switch_cell_type: coarse_grain in Liberty and design attribute

UPF_switch_cell_type coarse_grain in Unified Power Format (UPF) (see Table 4).

component: A physical and logical construction that relates inputs to outputs.

composite domain: A power domain consisting of subordinate power domains called subdomains. All

subdomains in a composite domain share the same primary supply set.

configuration UPF: A Unified Power Format (UPF) specification of the power-management configuration

for a system.

connected: Attached together via a direct connection.

constraint UPF: A Unified Power Format (UPF) specification for an intellectual property (IP) block that

defines constraints for any instance of this IP block that must be met by the power-management

configuration of the system containing that instance.

correlated: A pair of supply nets or a pair of supply sets that are deemed to be at the same point in their

voltage range when being considered for level-shifting. As such, when voltage levels are considered

between them they should be mutually compared, e.g., minimum to minimum and maximum to maximum.

corruption semantics: The rules defining the behavior of logic in response to reduction or disconnection

of power to that logic.

current scope: The design hierarchy location that serves as the immediate context for interpretation and

execution of Unified Power Format (UPF) commands. Also, the instance specified by the set_scope

command.

declared: Specified in the hardware description language (HDL) explicitly or implicitly via a Unified

Power Format (UPF) command.

descendant: Any instance between the current scope in the logic hierarchy and its leaf-level instances.

See also: ancestor.

descendant subtree: A portion of a logic hierarchy, rooted at one instance in the hierarchy, and

containing that instance and all of its descendants.

design hierarchy: A hierarchical structure of nested definitions described in a hardware description

language (HDL).

direct connection: A physical wire; or any hardware description language (HDL) construct(s) that

synthesize(s) to a direct connection.

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IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

domain port: A port that is on the interface of a power domain.

driver: The source or drain of a transistor, if the drain or source is connected to a power rail; a

complementary metal oxide semiconductor (CMOS) inverter that continually connects a node to power or

ground; any component that sets the value of its output via a transistor or inverter; a constant assignment;

any combinational logic including a buffer of any kind; any sequential logic; or any hardware description

language (HDL) construct(s) that synthesize(s) to such combinational or sequential logic.

driver supply: For a driver that is a transistor, the supply connected to its source or drain; for a driver that

is an inverter, the pair of supplies connected to the source/drain of the transistor pair comprising the

inverter; or for an output of an active component, the related supply set of that output.

electrically equivalent: For supply ports/nets, connected (whether the connections are evident or not in

the design) without any intervening switches, and therefore have the same value at all times from the

perspective of any load; for supply sets/set handles, consisting of a set of electrically equivalent supply

nets for each required function.

equivalent: A pair of supply nets, a pair of supply sets or a pair of logic nets that are considered to be

identical for certain purposes. See also: electrically equivalent; functionally equivalent.

erroneous: A usage that is likely to lead to an error in the design, but that tools may not be able to detect

and report.

extent (of a domain): The set of instances that comprise a power domain.

fanout domain (of a given port to which a given strategy applies): The power domain containing any of

the following: receiving logic for that port, or a leaf-level cell instance HighConn input port that is

connected to the given port, or a design top module LowConn output port that is connected to the given

port.

feedthrough: A direct connection between two ports on the interface of a power domain, where the

connection involves two ports on the upper boundary, or two ports on the lower boundary, or one of each;

also, a direction connection between two ports of the same leaf-level instance.

feedthrough port: A port on the interface of a power domain that is part of a feedthrough through that

domain, or a port on the interface of a leaf-level instance that is part of a feedthrough through that

instance.

fine grain switch: A power switch that is used to generate switched supply for a single library cell. This is

typically used to describe embedded macro power switches. This is identified using the attribute

switch_cell_type: fine_grain in Liberty and design attribute UPF_switch_cell_type fine_grain in

Unified Power Format (UPF) (see Table 4).

functionally equivalent: Functioning identically from the perspective of any load, either as a result of

being electrically equivalent, or due to independent but parallel circuitry. Can be defined as

interchangeable or non-interchangeable.

generate block: In the hardware description language (HDL) code, this represents a level of design

hierarchy, although a generate block is not itself an instance. After synthesis, generate blocks do not exist

as an independent level of hierarchy. It is illegal to create any Unified Power Format (UPF) objects in a

scope that corresponds to a generate block.

golden source: The design together with the constraint Unified Power Format (UPF) and the configuration

UPF.

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IEEE Standard for Design and Verification of Low-Power, Energy-Aware Electronic Systems

hard macro: An instance that has UPF_is_hard_macro attribute set to TRUE. This instance typically

represents a block that has been completely implemented and can be used as it is in other blocks. This can

be modeled by an hardware description language (HDL) module for verification or as a library cell for

implementation.

hierarchical name: A series of names separated by the hierarchical separator character, the final name

of which is a legal hardware description language (HDL) name or Unified Power Format (UPF) name, and

each preceding name is the name of an instance or generate block in which the following name is

declared. See also: hierarchical separator character.

hierarchical separator character: A special character used in composing hierarchical names. The

hierarchical separator character is a slash (/).

HighConn: The side of a port connection that is higher in the design hierarchy; the actual signal

associated with a formal port definition.

implementation UPF: The Unified Power Format (UPF) specification of how power distribution and

control is to be implemented for a system.

inactive: A normally active component in a state in which it does not respond to activity on its inputs.

Also, a control signal that is not currently presenting the value (level) or transition (edge) that enables or

triggers an active component to operate in a particular manner.

instance: A particular occurrence of a SystemVerilog module (see IEEE Std 1800), very high speed

integrated circuit (VHSIC) hardware description language (VHDL) entity (see IEC 61691-1-1/IEEE Std

1076), or library cell at a specific location within the design hierarchy.

interface of a power domain: The union of the upper boundary and the lower boundary of the power

domain.

isolation: A technique used to provide defined behavior of a logic signal when its driving logic is not

active.

isolation cell: An instance that passes logic values during normal mode operation and clamps its output to

some specified logic value when a control signal is asserted.

leaf cell: See: leaf-level cell.

leaf instance: See: leaf-level cell.

leaf-level cell: An instance that has no descendants, or an instance that is a soft or hard macro.

leaf-level instance: See: leaf-level cell.

level-shifter: An instance that translates signal values from an input voltage swing to a different output

voltage swing.

live slave: A retention element style in which the slave latch of a master-slave flip-flop (MSFF) is always

on and therefore maintains the value of the MSFF during power-down.

logically equivalent: Logic ports/nets that are directly connected without any intervening logic and

therefore have the same value at all times from the perspective of any sink.

logic hierarchy: An abstract view of a design hierarchy in which only those definitions representing

instances are included.

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