An Efficient CC-R-E-DVS Scheduling Algorithm and Its Simulation on
SIM-WATTCH
1
Manman Peng,
2
Pin Yu
1
Hunan University, Hunan, China, E-mail: pmmbysj@hnu.cn
2
Hunan University, Hunan, China, E-mail: yupinhnu@gmail.com
Abstract
Dynamic voltage scaling is an effective technique for power saving of processors. It adjusts the
supply voltage and the frequency of the processors dynamically, thus the power consumption can be
reduced. Based on the former research, we proposed an efficient DVS scheduling algorithm named
CC-R-E-DVS, which is a kind of EDF scheduling. The DVS we proposed can reasonably use the slack
time and reduce the computation cost as much as possible. In the best cases, it has a complexity of
O(n). We simulated several DVS algorithms and compared the performance with each other through
modeling a multicore environment on SIM-WATTCH
[1]
. The results show that the CC-R-E-DVS can
reduce power consumption by 10%~40% over CC-EDF-DVS
[2]
.
Keywords: DVS Scheduling, Complexity, Power Consumption
1. Introduction
With the development of the integrated circuits technology, the power densities of processors and
concomitant heat generation are rapidly approaching levels comparable to nuclear reactors
[3]
. Because
of the high power densities, how to improve the performance of processors is becoming more and more
difficult. And higher power consumption means more cooling costs, which is not what we expected. So
many researchers have devoted a lot of energy to seeking a better solution. Especially for the rapidly
increasing number of embedded devices, power consumption is attracting more and more attention.
How to reduce power consumption as much as possible with least performance decrease has been a hot
research topic.
In CMOS microprocessors, dynamic power consumption (P
d
) is the main source of power
consumption, which primarily arises from the charging and discharging of capacitors. Dynamic power
consumption Pd can be expressed as follows
[4]
:
CLK
2
DDLd
fVCP
. (1)
Here, α is the activity factor, C
L
is the load capacitance, V
DD
is the supply voltage, and f
CLK
is the
clock frequency. The relation between V
DD
and f
CLK
is given by (2) where κ is a constant, and V
th
is
the threshold voltage.
DD
2
thDD
CLK
V
)V-V
f
(
. (2)
So when V
DD
>> V
th
, f
CLK
is a linearly increasing function of V
DD
. Actually in most of the research
P
d
has been supposed to be expressed as (3).
3
DDLd
VCP
. (3)
Now it’s obvious that we can remarkably reduce power consumption by decreasing the supply
voltage. But the clock frequency will be turned down according to (2) and that would lead to
performance decreasing. However, in real time systems, all tasks are only required to finish before their
deadlines. As the execution time of the tasks is not fixed, the tasks usually finish much earlier before
their worst case execution time (WCET)
[5]
and the system gets into idle state. So we can lower down
the clock frequency at a proper time in order to make use of the slack time and reduce the power
consumption.
An Efficient CC-R-E-DVS Scheduling Algorithm and Its Simulation on SIM-WATTCH
Manman Peng, Pin Yu
International Journal of Advancements in Computing Technology(IJACT)
Volume4, Number9, May 2012
doi: 10.4156/ijact.vol4.issue9.25