纳米线隧道FET解析模型：理论与模拟验证

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本文主要探讨了纳米线隧道场效应晶体管(Nanowire Tunnel FETs, NW-TFETs)的解析模型，该研究在第11届紧凑建模国际研讨会中发表。作者 Ying Liu、Jin He 等来自北京大学深圳SOC实验室、PKU-HKUST深圳-香港联合机构、香港科技大学电子与计算机工程系以及深圳华越泰拉科技芯片电子有限公司的研究团队合作完成。纳米线隧道FET是一种先进的半导体器件，其采用硅纳米线作为通道，具有极小的尺寸和独特的门全包围(Gate-All-Around, GAA)结构，能够实现低功耗和高密度的逻辑功能。在这个研究中，作者们针对NW-TFET的工作原理，特别关注了表面电势解决方案以及带间隧穿(Band-to-Band Tunneling, BTBT)效应在器件性能中的关键作用。首先，研究团队通过三维泊松方程的求解，获得了沿通道方向的分区域表面电势分布。这一步骤对于理解电流控制机制至关重要，因为表面电势的变化直接影响着载流子的传输和隧道效应的发生。通过这种方法，他们能够准确地模拟和预测纳米线结构中电子的行为。接着，基于Kane表达式，他们开发了一种解析的隧道电流模型，该模型考虑了BTBT过程对电流的影响，从而能更精确地估计设备的开关速度和阈值电压。这种模型对于设计和优化NW-TFET的性能参数具有重要的指导意义，因为它提供了一种理论框架，可以与计算机辅助设计(Circuit Simulation)工具，如TCAD（Technology Computer-Aided Design），进行有效的比较和验证。通过将模型的预测与TCAD仿真结果进行对比，研究者证明了所提出的解析模型的有效性。这种模型不仅有助于深入理解NW-TFET的内部工作原理，而且为纳米尺度器件的设计提供了重要的理论支持。关键词包括GAA结构、纳米线隧道FETs以及相关的数值模拟技术，这些研究成果对于推动纳米电子学领域的发展具有显著贡献。这篇论文提供了一个完整的纳米线隧道FET的理论分析框架，对未来纳米器件的高性能和小型化具有重要的参考价值。

11th international Workshop on Compact Modeling 19

An Analytic Model for Nanowire Tunnel-FETs

Ying Liu

, Jin He

1,*

Mansun Chan

, Caixia Du

, Yun Ye

, Wei Zhao

, Wen Wu

, and Wenping Wang

Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen-Hong Kong Institution, Shenzhen, China

Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Kowloon, Hong Kong

Shenzhen Huayue Teracale Chip Electronic Limited Co., Shenzhen, China

Abstract

—

In this paper, an analytical model of the

gate-all-around (GAA) silicon nanowire tunnel-FETs

(NW-TFETs) is proposed based on the surface potential

solutions at the channel direction and considering band to band

tunneling (BTBT) efficiency. The 3-D Poisson’s equation is

solved to obtain the surface potential distribution in the partition

regions along the channel direction for NW-TFET device and

then a tunneling current model using Kane’s expression is

developed. The validity of the developed model is proved by the

good agreement between the model predictions and TCAD

simulation results.

Keywords — Gate-All-Around (GAA); nanowire tunnel-FETs

(NW-TFETs); band to band tunneling (BTBT); analytic model.

I. INTRODUCTION

unnel-FETs (TFET) has been got great attention in the

semiconductor academic and industry fields in recent

years for the superior performance in sub-threshold region.

Compared with the conventional MOSFETs, TFET is

competitive and chosen due to its high ON-OFF current ratio,

below 60 mV/dec sub-threshold swing (SS) and low leakage

power consumption [1]. However, TFETs have a small

amount of band to band tunneling (BTBT) efficiency in the

large band gap of silicon body leading to a low ON-current.

To obtain the high ON-current and small SS, the GAA

NW-TFETs are considered as an efficient device candidate. In

recent several years, NW-TFET process technology and

fabrication measures have been matured, many research

papers have been published so far [6]-[8]. However, the

compact model of NW-TFET for circuit performance

prediction and simulation has made a few progress，Most

works only focus on NW-TFET empirical model development

[6],[9],[12]]. So far, there is no a complete analytical model of

GAA NW-TFET for device scientists and circuit designers to

test and simulation such a device based circuit performance.

In this paper, an analytical model of GAA silicon

NW-TFETs has been developed based on the

three-dimensional (3-D) potential solution and the Kane’s

expression. For the purpose of observing the validity of the

model and the different structure parameter impact on the

device performance, we have also compared the analytical

model prediction with the TCAD SenTaurus simulation

results of the device to verify the model validity.

II. STRUCTURE AND MODEL

A. Structure of GAA NW-TFET

The Fig.1 shows the structure of GAA TFET with silicon

nanowire body. As is shown in Fig.1.(a), the source

electrode length is

(10nm), the drain electrode length

(10nm), the gate electrode length is

(50nm), the

oxide (

SiO

) thickness is

and the channel radium is

Fig.1. (b) shows the cross-section of the device with

n-channel. In this paper, the n-TFET is considered so that

the doping profile along the axis direction of the nanowire

with the



doping in source (

20 3

N cm







doping in

channel (

10 3

N cm





) and



doping in drain

(

20 3

N cm





). Band-to band tunneling (BTBT) happens

in the P-N junction at the source-channel region. Based on

the drift-diffusion (DD) theory, the electrons are moved

toward the drain thus the device can be divided into three

regions: the depletion region Ⅰ (

0Lx  

), the

tunneling region Ⅱ (

0 xL

) and the surplus channel

region Ⅲ (

2 g

L x L

Fig.1. (a) 3-D structure of the n-channel GAA Silicon NW-TFET (b)

Cross-section of the device and its division into a depletion region (Ⅰ), a

tunneling region (Ⅱ) and a conventional GAA MOSFET region (Ⅲ).

(a)

Drain

Gate

Source

(b)

Depletion

Tunneling

Source

P+

Gate Metal

Drain

N+

Oxide

Ⅱ

Ⅰ

Channel N+

Ⅲ

L

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