动态可变FIR滤波器：1.3GHz高通量低延迟设计

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本文主要探讨了一种高性能的数字有限 impulse response (FIR) 滤波器的设计，特别针对现代硬盘驱动器中的部分响应最大似然 (PRML) 读取通道。这种滤波器采用了一种混合同步-异步架构，旨在实现高吞吐量和低延迟。在设计上，该FIR滤波器的关键部分采用了高效的异步流水线结构。这种异步设计允许滤波器处理速度得到显著提升，同时保持了对时钟同步环境的良好兼容性。这使得整个滤波器能够在严格的时钟控制下工作，适应不同数据传输速率的需求。一个创新的特点是，滤波器的流水线深度是动态可变的。这意味着，根据输入数据的实时速率，系统能够自动调整流水线长度，从而优化性能和资源利用率。这种自适应特性对于现代数据处理系统来说，是非常重要的，因为它能够实时地根据数据流量的变化进行调整，以保证系统的稳定性和效率。设计团队由来自多个知名学府和研究机构的专家组成，包括北卡罗来纳大学教堂山分校、IBM托马斯·沃森研究中心以及哥伦比亚大学的计算机科学部门，他们的研究展示了在高级磁盘驱动技术中，如何通过创新的数字信号处理方法来提升存储设备的性能。这篇论文提供了一个具有挑战性的解决方案，它不仅展示了如何将异步计算的优势与同步接口相结合，而且还引入了动态流水线管理的概念，这对于现代电子系统设计，尤其是在高速数据处理领域，具有重要的理论价值和实际应用潜力。通过深入理解并借鉴本文的研究成果，工程师们可以更好地设计出能满足高速、低延迟要求的数字滤波器，推动信息技术的进一步发展。

Req

Stage

Controller

eval

matched

delay

Stage

Controller

eval

matched

delay

Stage

Controller

eval

matched

delay

Req

DoneDoneDone

Figure 1. Block diagram of an HC pipeline

5-bit address word and only 32 entries. This represents a

dramatic reduction in the size of memory required, from

one 1024 entry table, to two 32 entry tables. However, there

is a slight tradeoff: twice the number of partial sums are

generated, requiring an additional adder stage to combine

them.

Exploiting Symmetry. To further reduce the table size in

half, a data representation scheme is used that makes the ta-

ble symmetric. In particular, the signed-digit offset binary

notation [8] is used, in which the symbols “0” and “1” stand

for negative and positive exponents of 2. For example, in

this notation, the 4-bit number “1001” stands for the value

8 − 4 − 2+1=3. The advantage of this representation is

that arithmetic negation is simply achieved by complement-

ing each bit: “0110” stands for the value −3. An interesting

feature of the ﬁlter equation (Equation 1) is that, if all the

inputs are negated, the ﬁlter output is also negated. Con-

sequently, when this representation is used, if two address

words for the lookup table are bit-wise complements of each

other, then the corresponding table entries will also be bit-

wise complements of each other. Exploiting this symmetry,

half of the table can be discarded.

2.2. High-Capacity Asynchronous Pipelines

This subsection reviews the pipelining approach adapted

for the asynchronous portion of the ﬁlter chip. A class

of pipelines, called high-capacity (

HC), is used, which are

targeted to dynamic logic implementations [12]. They are

based on a novel protocol that maximizes the pipeline stor-

age capacity by allowing every dynamic stage to hold a

distinct data item. In contrast, in traditional latch-free

asynchronous dynamic pipelines (e.g., [18, 13]), alternat-

ing stages usually must contain “spacers,” or “reset tokens,”

limiting the pipeline capacity to 50%.

The key idea in the

HC approach is one of decou-

pled control: the pull-up and pull-down of the dynamic

gates are made separately controllable. Therefore, the

precharge and evaluate controls can both be simultaneously

de-asserted, allowing the gate to enter a special “isolate

phase”—between “evaluation” and “precharge”—in which

its output is protected from further input changes. As a re-

sult, every pipeline stage can store a distinct data item, pro-

viding the capability of supporting 100% storage capacity.

In addition, the decoupled control leads to increased over-

all pipeline concurrency which in turn directly results in a

signiﬁcantly increased throughput.

2.2.1. Structure

Figure 1 shows a simple block diagram of an

HC pipeline.

Each stage consists of three components: a function block, a

completion generator and a stage controller. In steady-state

operation, the function block alternately produces data to-

kens and reset spacers for the next stage, and its completion

generator indicates completion of the stage’s evaluation or

precharge. The third component, the stage controller, gen-

erates the decoupled control signals—pc and eval—which

control the function block and the completion generator.

HC pipelines use a single-rail bundled datapath [11, 1].

A control signal, Req, indicates arrival of new inputs to a

stage. A high value of Req indicates the arrival of new data:

the previous stage has completed evaluation. A low Req in-

dicates the arrival of a spacer: the previous stage has com-

pleted precharge. For correct operation, a simple timing

constraint must be satisﬁed: Req must arrive after the data

inputs to the stage are stable and valid. This requirement is

met by inserting a “matched delay” which is greater than or

equal to the worst-case delay through the function block.

Function Block. Figure 2 shows one gate of a dynamic

function block in a pipeline stage. In general, for a multiple

output function block, there will be one such dynamic gate

for each output.

The pc input controls the pull-up network

and the eval input controls the “foot” of the pull-down net-

work. Precharge occurs when pc is asserted low and eval

is de-asserted low. Evaluation occurs when eval is asserted

high and pc is de-asserted high. In

HC pipelines, the two

control signals, pc and eval, are separately generated and are

decoupled. Therefore, when both signals are de-asserted,

the gate output is effectively isolated from the gate inputs;

For complex logic, where a single dynamic gate would be too large

and slow, decomposition into a multi-level monotonic network is used.

Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC’02)

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动态可变FIR滤波器：1.3GHz高通量低延迟设计

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