Semtech GS2972：3G/HD/SD-SDI serializer with comprehensive SMPTE audio/video support

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Semtech-GS2972是一款高度集成的3G/HD/SD-SDI serializer，专为满足专业音频视频应用的需求而设计。该器件在数据速率上具有灵活性，支持2.970 Gb/s、2.970/1.001 Gb/s、1.485 Gb/s、1.485/1.001 Gb/s 和 270 Mb/s等多种标准，适用于多种通信标准，如SMPTE T425 Level A和Level B（包括SMPTE T424、T292、T259-C和DVB-ASI）。 GS2972的核心特性包括内置电缆驱动器，提供稳定的信号传输；一个低噪声的电压控制振荡器（VCO），确保频率稳定；以及一个窄带宽锁相环（PLL），有助于保持时钟精度。对于音频处理，它具备内置音频嵌入器，能够支持高达8通道的48kHz音频，满足高保真音频的需求。此外，该器件还支持 Ancillary data insertion 功能，能够在视频信号中插入额外的数据信息。对于1080p50/60 4:2:2 10-bit格式，提供了可选的SMPTE T425 Level A到Level B转换，便于信号升级或兼容性处理。数据接口可以选择为20-bit或10-bit模式，以适应不同的应用需求。视频处理方面，GS2972集成了TRS计算和插入、行号计算和插入、基于行的CRC计算和插入、非法码重新映射、SMPTE T352 payload identifier生成和插入等功能，确保视频信号的完整性和准确性。其内部还包含GSPI主机接口，便于与外部设备进行高效通信。供电方面，GS2972采用+1.2 V数字核心电源，以及+1.2 V和+3.3 V的模拟电源，同时I/O电源支持可选的+1.8 V或+3.3 V，为不同工作环境和功耗优化提供了灵活性。工作温度范围宽广，从-20°C至+85°C，确保在各种严酷条件下稳定运行。 Semtech-GS2972是一款高性能且功能丰富的3G/HD/SDI串行器，广泛应用于专业电视广播、视频监控、多媒体系统等对音频视频质量要求较高的领域，通过其全面的特性组合满足了现代通信和多媒体处理的复杂需求。

GS2972 3G/HD/SD-SDI Serializer with Complete

SMPTE Audio & Video Support

Final Data Sheet Rev. 9

GENDOC-047479 September 2013

16 of 125

www.semtech.com

G6 SMPTE_BYPASS Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to enable / disable all forms of encoding / decoding,

scrambling and EDH insertion.

When set LOW, the device operates in data through mode

(DVB_ASI= LOW), or in DVB-ASI mode (DVB_ASI = HIGH).

No SMPTE scramblin

g takes place and none of the I/O processing

features of the device are available when SMPTE_BYPASS

is set

LOW.

When set HIGH, the device carries out SMPTE scrambling and I/O

processing.

G7IOPROC_EN/DIS

Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to enable or disable the I/O processing features.

When IOPROC_EN/DIS is HIGH, the I/O processing features of the

device are enabled. When IOPROC_EN/DIS

is LOW, the I/O processing

features of the device are disabled.

Only applicable in SMPTE mode.

G8RESET

Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to reset the internal operating conditions to default settings

and to reset the JTAG sequence.

Normal mode (JTAG/HOST

= LOW).

When LOW, all functional blocks will be set to default conditions

and all input and output signals become high impedance.

When HIGH, normal operation of the device resumes.

JTAG test mode (JTAG/HOST

= HIGH).

When LOW, all functional blocks will be set to default and the JTAG

test sequence will be reset.

When HIGH, normal operation of the JTAG test sequence resumes.

H3 ANC_BLANK

Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

When ANC_BLANK

is LOW, the Luma and Chroma input data is set

to the appropriate blanking levels during the H and V blanking

intervals.

When ANC_BLANK

is HIGH, the Luma and Chroma data pass

through the device unaltered.

Only applicable in SMPTE mode.

H4 LOCKED Output

STATUS SIGNAL OUTPUT.

Please refer to the Output Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

PLL lock indication.

HIGH indicates PLL is locked.

LOW indicates PLL is not locked.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS2972 3G/HD/SD-SDI Serializer with Complete

SMPTE Audio & Video Support

Final Data Sheet Rev. 9

GENDOC-047479 September 2013

17 of 125

www.semtech.com

H5 GRP2_EN/DIS Input

Enables Audio Group 2 embedding. Set HIGH to enable.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

H6GRP1_EN/DIS

Input

Enables Audio Group 1 embedding. Set HIGH to enable.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

H7 AUDIO_INT Output

STATUS SIGNAL OUTPUT.

Please refer to the Output Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Summary Interrupt from Audio Processin

This signal is set HIGH by the device to indicate a problem with the

audio processing which requires the Host processor to interrogate

the interrupt status registers.

IO_VDD = +3.3V

Drive Strength = 8mA

IO_VDD = +1.8V

Drive Strength = 4mA

Note: By default, out of reset, the AUDIO_INT pin will output the

HD_AUDIO_CLOCK, rather than the audio interrupt signal. In order

to output the interrupt flags from the audio core as intended, the

user must write 0001h to register 0232h.

H8 JTAG/HOST

Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to select JTAG test mode or host interface mode.

When JTAG/HOST is HIGH, the host interface port is configured for

JTAG test.

When JTAG/HOST is LOW, normal operation of the host interface

port resumes and the separate JTAG pins become the JTAG port.

J4AIN_5/6 Input

Serial Audio Input; Channels 5 and 6.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

J5WCLK2 Input

48kHz Word Clock associated with AIN_5/6 and AIN_7/8 (channels 5,

6, 7 and 8).

Please refer to the Input Logic parameters in the DC Electric

Characteristics table for logic level threshold and compatibility.

J6 AIN_1/2 Input

Serial Audio Input; Channels 1 and 2.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

J7WCLK1 Input

48kHz Word Clock associated with AIN_1/2 and AIN_3/4 (channels 1,

2, 3 and 4).

Please refer to the Input Logic parameters in the DC Electrical

Chara

cteristics table for logic level threshold and compatibility.

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

GS2972 3G/HD/SD-SDI Serializer with Complete

SMPTE Audio & Video Support

Final Data Sheet Rev. 9

GENDOC-047479 September 2013

18 of 125

www.semtech.com

J8TCK Input

COMMUNICATION SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

JTAG Serial Data Clock Signal.

This pin is the JTAG clock when the JTAG/HOST pin is LOW.

J9 SDOUT_TDO Output

COMMUNICATION SIGNAL OUTPUT.

Please refer to the Output Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Shared JTAG/HOST

pin. Provided for compatibility with the GS1582.

Serial Data Output/Test Data Output.

Host Mode (JTAG/HOST

= LOW)

This pin operates as the host interface serial output, used to read

status and configuration information from the internal registers of

the device.

JTAG Test Mode (JTAG/HOST

= HIGH)

This pin is used to shift test results and operates as the JTAG test

data output, TDO (for new designs, use the dedicated JTAG port).

Note: If the host interface is not being used leave this pin

unconnected.

IO_VDD = +3.3V

Drive Strength = 12mA

IO_VDD = +1.8V

Drive Strength = 4mA

J10 SCLK_TCK Input

COMMUNICATION SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshol

d and compatibility.

Shared JTAG/HOST pin. Provided for pin compatibility with GS1582.

Serial data clock signal.

Host Mode (JTAG/HOST

= LOW)

SCLK_TCK operates as the host interface burst clock, SCLK.

Command and data read/write words are clocked into the device

synchronously with this clock.

JTAG Test Mode (JTAG/HOST

= HIGH)

This pin is the TEST MODE START pin, used to control the operation

of the JTAG test clock, TCK (for new designs, use the dedicated JTAG

port).

Note: If the host interface is not being used, tie this pin HIGH.

K4 AIN_7/8 Input Serial Audio Input; Channels 7 and 8.

K5 ACLK2 Input

64 x WCLK associated with AIN_5/6 and AIN_7/8 (channels 5, 6, 7 and

8).

K6 AIN_3/4 Input Serial Audio Input; Channels 3 and 4.

K7 ACLK1 Input

64 x WC

LK associated with AIN_1/2 and AIN_3/4 (channels 1, 2, 3and

4).

Table 1-1: Pin Descriptions (Continued)

Number

Name Timing Typ e Description

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