JESD84-A441: 2010年嵌入式多媒体卡规范

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"JESD84-A441 是JEDEC固态技术协会在2010年3月发布的一份规范手册，主要针对嵌入式多媒体卡(eMMC)的高容量、可靠写入、启动模式、双数据速率、多分区支持、安全性增强、后台操作和高优先级中断等功能进行了详细定义。该标准旨在促进制造商和购买者之间的理解和互换性，推动产品的改进，并帮助购买者快速选择和获取适用的产品，无论是国内还是国际使用。" JESD84-A441是JEDEC（Joint Electron Device Engineering Council）制定的一项标准，它定义了嵌入式多媒体卡(eMMC)的规范。这个标准是在2010年3月发布的，主要关注于高容量的eMMC产品，这些产品具有多种先进的功能，以满足现代电子设备的需求。 1. **可靠写入**: 这一特性确保在存储数据时的稳定性，减少数据丢失或损坏的风险，对于需要长期保存关键信息的设备尤其重要。 2. **启动模式**: eMMC支持特定的启动模式，使得设备能够快速从休眠状态恢复到工作状态，这对于移动设备和嵌入式系统来说是至关重要的。 3. **双数据速率**: eMMC支持双数据速率传输，意味着数据可以在上升沿和下降沿同时读写，显著提高了数据传输速度，提升了系统的整体性能。 4. **多分区支持**: JESD84-A441规范允许eMMC存储设备划分多个独立的逻辑分区，每个分区可以有不同的访问权限和用途，例如操作系统分区、应用程序分区和用户数据分区。 5. **安全性增强**: 标准包含了安全功能，可能包括加密、访问控制等，以保护存储在eMMC中的敏感信息不被非法访问或篡改。 6. **后台操作**: eMMC可以进行后台操作，这意味着在执行其他任务的同时，数据的读写和管理可以后台进行，不影响用户体验。 7. **高优先级中断**: 设计有高优先级中断功能，当有紧急任务需要处理时，系统可以立即响应，确保关键操作的及时完成。通过JESD84-A441标准，JEDEC致力于消除制造商与购买者之间的误解，促进不同设备间的互换性，并推动行业的持续进步。该标准的实施不受任何专利或其他知识产权的影响，鼓励创新并确保所有利益相关者都能受益。

JEDEC Standard No. 84-A441

-xii-

Embedded MultiMediaCard(e•MMC) e•MMC/Card Product Standard, High Capacity,

including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports,

Security Enhancement, Background Operation and High Priority Interrupt (MMCA, 4.41)

CONTENTS(continued)

Page

Figure 43 — Stop transmission after last data block; card is busy programming ................................ 107

Figure 44 — Stop transmission after last data block; card becomes busy............................................ 107

Figure 45 — Bus test procedure timing ................................................................................................ 108

Figure 46 — Boot operation, termination between consecutive data blocks........................................ 108

Figure 47 — Boot operation, termination during transfer .................................................................... 109

Figure 48 — Bus mode change timing (push-pull to open-drain) ........................................................ 109

Figure 49 — Alternative boot operation, termination between consecutive data blocks...................... 110

Figure 50 — Alternative boot operation, termination during transfer .................................................. 110

Figure 51 — H/W reset waveform........................................................................................................ 112

Figure 52 — Noise filtering timing for H/W reset................................................................................ 112

Figure 53 — CRC7 generator/checker.................................................................................................. 158

Figure 54 — CRC16 generator/checker................................................................................................ 159

Figure 55 — Bus circuitry diagram....................................................................................................... 163

Figure 56 — Improper power supply.................................................................................................... 164

Figure 57 — Shortcut protection........................................................................................................... 164

Figure 58 — Power-up diagram............................................................................................................ 165

Figure 59 — e•MMC power-up diagram ..............................................................................................167

Figure 60 — The e•MMC power cycle................................................................................................. 168

Figure 61 — MultiMediaCard bus driver ............................................................................................. 170

Figure 62 — e•MMC internal power diagram ...................................................................................... 172

Figure 63 — Bus signal levels .............................................................................................................. 174

Figure 64 — Timing diagram: data input/output .................................................................................. 176

Figure 65 — Timing diagram: data input/output in dual data rate mode.............................................. 179

Figure A.1 — Power supply decoupling................................................................................................. 185

Figure A.2 — Modified MultiMediaCard connector for hot insertion ................................................... 186

Figure A.3 — Legend for command-sequence flow charts .................................................................... 189

Figure A.4 — SEND_OP_COND command flow chart ........................................................................ 190

Figure A.5 — CIM_SINGLE_CARD_ACQ .......................................................................................... 191

Figure A.6 — CIM_SETUP_CARD....................................................................................................... 192

Figure A.7 — CIM_STREAM_READ................................................................................................... 193

Figure A.8 — CIM_READ_BLOCK ..................................................................................................... 193

Figure A.9 — CIM_READ_MBLOCK.................................................................................................. 194

Figure A.10 — CIM_WRITE_MBLOCK ................................................................................................ 195

Figure A.11 — CIM_ERASE_GROUP.................................................................................................... 196

Figure A.12 — CIM_SECURE_ERASE..................................................................................................197

Figure A.13 — CIM_SECURE_TRIM..................................................................................................... 198

Figure A.14 — CIM_TRIM...................................................................................................................... 199

Figure A.15 — CIM_US_PWR_WP ........................................................................................................ 200

Figure A.16 — CIM_US_PERM_WP...................................................................................................... 201

Figure A.17 — Bus testing for eight data lines......................................................................................... 205

Figure A.18 — Bus testing for four data lines .......................................................................................... 205

Figure A.19 — Bus testing for one data line ............................................................................................ 205

Figure A.20 — Erase-unit size selection flow .......................................................................................... 207

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