H.264/AVC标准熵编码技术解析

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"熵编码在H.264/AVC标准中的应用与算法及VLSI架构" 熵编码是数字视频编码技术中的关键部分，特别是在H.264/AVC标准中，它极大地提高了数据压缩效率。H.264/AVC，全称为高级视频编码（Advanced Video Coding），是由国际电信联盟（ITU-T）的视频编码专家组（VCEG）和国际标准化组织（ISO）的运动图像专家组（MPEG）联合制定的视频压缩标准。该标准旨在提供更高的压缩比，以满足对高清视频传输和存储的需求。熵编码是熵编码器的主要任务，其目标是将经过预测和变换等预处理步骤后的视频数据进行有损或无损的高效编码。H.264/AVC标准中主要采用了两种熵编码技术：游程编码（Run-Length Encoding, RLE）和熵变长编码（Variable Length Coding, VLC）。 1. 游程编码：主要用于处理连续的相同像素值。当视频帧中有大量连续相同的颜色时，游程编码可以有效地表示这种模式，通过记录连续像素值的个数和该值本身来减少数据量。 2. 熵变长编码：H.264/AVC中采用的主要熵编码器是熵上下文适应二进制算术编码（Context-Adaptive Binary Arithmetic Coding, CABAC）和熵上下文适应变量长度编码（Context-Adaptive Variable Length Coding, CAVLC）。这两种编码方式都是基于熵编码原理，根据当前编码符号的概率分布进行编码，其中概率高的符号用较短的码字表示，概率低的符号用较长的码字表示。CABAC提供了更高的编码效率，但计算复杂度相对较高，而CAVLC则较为简单，适用于实时编码。 3. CABAC（上下文适应算术编码）：CABAC使用算术编码方法，结合了上下文信息，动态地调整编码的精度，以更精确地适应数据的统计特性。每个编码符号的上下文是由之前编码的符号决定的，从而提高编码效率。 4. CAVLC（上下文适应变长编码）：虽然没有CABAC那样高效，但CAVLC的实现更为简单，编码过程不需要复杂的算术运算，更适合硬件实现。它利用了前导零的数量和系数的极性来决定码字的长度。熵编码在H.264/AVC标准中扮演着至关重要的角色，不仅在提高压缩效率方面表现出色，而且对于不同应用场景提供了灵活的选择。同时，为了实现这些编码技术，需要设计高效的VLSI（Very Large Scale Integration）架构，以满足实时编码和解码的需求。这些架构通常需要考虑功耗、面积和速度等多个因素，以实现最优的性能与能效比。熵编码在H.264/AVC标准中的应用，包括游程编码、CABAC和CAVLC，以及相应的VLSI架构设计，都是现代数字视频编码领域的重要研究方向。这些技术的发展推动了视频通信、网络流媒体和存储系统等领域的大规模进步。

List of Figures

1.1 YUV sampling schemes ....................... 5

1.2 Forward DCT ﬂow graph for N = 8, Ci = cos i, Si = sin i

[Chen77, Rao90] ........................... 7

1.3 Scanning order of residual blocks within a macroblock . . . .... 8

1.4 3-stage 1-D DWT decomposition using pyramid algorithm

[Mallat89]............................... 11

1.5 Three-level 2-D wavelet decomposition . . ............. 12

1.6 The block matching process . . . .................. 15

1.7 Grid-based block matching process ................. 16

1.8 Three-step search [Koga81] . . . .................. 17

1.9 Simpleandefﬁcientsearch ...................... 18

1.10 Pixel decimation and motion ﬁeld .................. 19

1.11 An 8 × 8 transformed block is zig-zag scanned into a 1 × 64

vector with the largest values – in magnitude – concentrating

atthebeginningofthe1-Dvector .................. 21

1.12 Coding interval subdivision of binary arithmetic coding . . . .... 23

1.13 Block diagram of MB processing in H.264/AVC. (a)MB

encoding, (b) MB decoding . . . .................. 26

1.14 MB partition modes and sub-MB partition modes of ME

in H.264/AVC . ............................ 27

2.1 CAVLC encoding of one transform coefﬁcient block

[Richardson03] ............................ 30

2.2 Flowchart for CAVLC codec: (a) Decoder and (b) Encoder . .... 30

2.3 Bit assignment of low and range in QM coder of JPEG . . . .... 32

2.4 Block diagram of the CABAC encoder of H.264/AVC . . . .... 34

2.5 Coding interval subdivision and selection procedure

ofCABAC .............................. 37

2.6 Coding interval subdivision and selection of regular bin

ofCABAC .............................. 37

2.7 Pseudo C-program of renormalization and bit output

ofCABAC .............................. 38

2.8 Decision of bit output and accumulation of outstanding

(OS)bit ................................ 38

xvi List of Figures

3.1 CAVLD architecture [Chang05] with direct implementations

of functional blocks . . . ....................... 44

3.2 Five decoding stages of the CAVLD architecture [Alle06] . .... 44

3.3 Fast leading zero detection circuit [Alle06] ............. 45

3.4 The CAVLD architecture [Lin08a] .................. 46

3.5 Modiﬁed level decoding process [Lin08a] . ............. 47

3.6 Block diagram of CAVLC [Kim06a] ................. 50

3.7 Block diagram of H.264/AVC Baseline proﬁle entropy

coding ﬂow . . ............................ 51

3.8 (a) Dual-buffer encoder architecture and (b) two-stage

pipeline of block scanning and coding of [Chen06c] ........ 51

3.9 Side information aided symbol look ahead structure of

[Tsai06] ................................ 52

3.10 Example of a 4×4 residual block in the CAVLC procedure . .... 52

3.11 Example of the proposed SIA ﬂags deﬁnition [Tsai06] . . . .... 53

3.12 Architecture of the ATE for level code generation

[Rahman07] . . ............................ 54

3.13 Block diagram of CABAC decoder .................. 57

3.14 Double-bin decoding architecture of [Yu05] ............. 59

3.15 Map of context models of context RAM [Chen07a] . ........ 59

3.16 Four-stage CABAC decoding pipeline of [Shi08] . . ........ 61

3.17 Rate-distortion optimization assisted CABAC encoding with

circuits of context state backup and restoration [Nunez06] . .... 64

3.18 Arithmetic coding interval update with double bins per cycle

throughput [Osorio06] . ....................... 65

4.1 Design ﬂow for an SoC-based entropy coder ............. 72

4.2 Five CABAC functional categories as % of total CABAC

instructions in CIF test of H.264/AVC encoder of JM

reference SW in the QP range of 12–36 . . ............. 75

4.3 Five HW/SW partitioning schemes of CABAC encoding . . .... 77

4.4 FSM-based partitioning scheme for HW CABAC encoder . .... 81

4.5 The proposed partitioning scheme for HW CABAC encoder .... 82

4.6 Block diagram of top-level architecture of HW CABAC

encoder ................................ 85

4.7 Input packet format of CABAC encoder . . ............. 87

4.8 Procedure for parsing and binarization non-/residual SE and

control parameters of unit BN, Block 1 . . ............. 88

4.9 HW-orientedEGkbinarizationalgorithm .............. 90

4.10 Fast EGk binarization implementaion. (a) EG3 binarization

forthesufﬁxofMVD;(b) EG0 binarization for the sufﬁx of

abs_level_minus1........................... 90

4.11 Architecture of unit BS&CS2: (a) CtxIdx calculation and

bin packet serial output circuit for all SE, excluding SCF and

LSCF; (b) CtxIdx calculation and SE serial output of SCF

and LSCF packet of residual coefﬁcient block ............ 91

List of Figures xvii

4.12 Flowchart of renormalization and bit packing algorithm

inHW................................. 93

4.13 Three-stage pipeline implementation of renormalization

and bit packing algorithm in unit AR and unit BP . . ........ 94

4.14 ArchitectureofunitAR........................ 95

4.15 Two-stage design of bit packing . .................. 96

5.1 BlockdiagramofunitCS1,withsub-unitsMAandIC ....... 100

5.2 Reference MBs on top and left of current MB, and storage

of 3 categories of coded SEs (MB, 8×8 sub-MB, and 4×4

block) in the referenced BPMB of the current and referenced

MBs.................................. 101

5.3 Fast access of neighboring coded block and sub-MBs. (a)

Access of neighboring luma 4×4 blocks, and (b) access of

neighboring 8×8 sub-MBs and chroma 4×4 blocks of 4:2:0

samplingformat ........................... 102

5.4 Functions of IC sub-unit of unit CS1 ................. 106

5.5 MB processing in MA sub-unit and IC sub-unit of unit CS

..... 110

5.6 Operations of MA sub-unit in the ﬁrst 3 cycles of MB

N, M−1

processing............................... 111

5.7 Architecture of unit CA with pipelined context line access

and local buffering scheme ...................... 113

5.8 Architecture of memory access control of unit CA in both

RDO-offandRDO-onmode ..................... 115

5.9 Reallocation of context model in context RAM (Normal

RAM). Context models of Normal RAM are illustrated as

two continuous parts in the ﬁgure .................. 116

5.10 Four types of pipelined context state backup and restoration

operation in P8×8 RDO coding . .................. 118

6.1 Wishbone-based point-to-point inter-connection of single

masterandslave ........................... 124

6.2 One classic cycle of a WISHBONE master interface

with registered feedback of cycle termination [Wishbone] . . .... 128

6.3 Illustration of constant address burst cycle of WISHBONE

slave interface [Wishbone] ...................... 129

6.4 Data output control of WISHBONE master interface

with 32-bit dat_o bus ......................... 131

6.5 Data output control of WISHBONE master interface

with 8-bit dat_o bus ......................... 131

6.6 Top-level architecture of 4-channel crossbar INTERCON

ofWISHBONEsystembus...................... 133

6.7 Round-robin arbitration of system bus master that connects

totheslave .............................. 134

6.8 Architecture of M0 sub-unit: (a) Generation of cyc signals

of 4 slaves that can connect to the master, and (b) selection

of master input signal including dat_i and ack_i ........... 135

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