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首页TM4C123GH6PM英文资料:Tiva Microcontroller DATASHEET
本文档是TI官方提供的TM4C123GH6PM微控制器的数据手册,适用于使用EK-TM4C123GXL开发板的开发者。TM4C123GH6PMMicrocontroller是一款由ARM架构的32位单片机,由Texas Instruments (TI)公司设计,专为工业级应用和高性能系统设计而优化。该文档详细列出了TM4C123GH6PMS的核心特性、引脚配置、寄存器结构、内存布局、外设接口、功耗特性和工作模式等内容。
核心知识点包括:
1. **硬件平台**:
- TM4C123GH6PMS基于ARM Cortex-M4内核,提供了高效的处理能力,支持Thumb-2指令集,以优化代码密度。
- 该单片机集成了丰富的功能,如DMA控制器、USB Host和Device接口、CAN、SPI、I2C等通信接口,以及定时器和计数器。
2. **电源管理**:
- 数据手册涵盖了电源管理特性,包括不同电压范围下的工作模式选择(如低功耗模式、待机模式等),以及电源转换和管理策略。
3. **外设接口**:
- 描述了各个外设的详细功能和操作方法,如ADC、DAC、GPIO、UART、PWM等,有助于用户了解如何配置和使用这些接口进行数据采集、通信和控制。
4. **编程和调试**:
- 提供了软件开发工具包(TivaWare)的概述,包括IDE支持、编译器信息以及调试接口说明,这对于使用Keil、IAR等集成开发环境的开发者很有帮助。
5. **生产与标准保修**:
- 数据手册明确了产品生产时的状态和测试标准,以及标准保修政策,用户在实际应用中应参考此信息以确保产品的性能和可靠性。
6. **注意事项与免责声明**:
- 文档结尾包含关于产品可用性、标准保修范围以及在关键应用中的使用限制和免责声明,这是用户在设计项目时必须了解的重要法律信息。
TM4C123GH6PM英文资料是开发和维护基于该芯片的系统项目的宝贵资源,为设计者提供了全面的技术指南,包括硬件特性、驱动编程和系统集成的方方面面。
Table 16-4. Inter-Integrated Circuit (I
2
C) Interface Register Map ........................................... 1014
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1020
Table 17-1. Controller Area Network Signals (64LQFP) ........................................................ 1047
Table 17-2. Message Object Configurations ........................................................................ 1052
Table 17-3. CAN Protocol Ranges ...................................................................................... 1060
Table 17-4. CANBIT Register Values .................................................................................. 1060
Table 17-5. CAN Register Map ........................................................................................... 1064
Table 18-1. USB Signals (64LQFP) .................................................................................... 1098
Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1109
Table 18-3. Actual Bytes Read ........................................................................................... 1109
Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1110
Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1111
Table 19-1. Analog Comparators Signals (64LQFP) ............................................................. 1212
Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1214
Table 19-3. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1215
Table 19-4. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1215
Table 19-5. Analog Comparators Register Map ................................................................... 1216
Table 20-1. PWM Signals (64LQFP) ................................................................................... 1229
Table 20-2. PWM Register Map .......................................................................................... 1236
Table 21-1. QEI Signals (64LQFP) ...................................................................................... 1303
Table 21-2. QEI Register Map ............................................................................................ 1307
Table 23-1. GPIO Pins With Default Alternate Functions ...................................................... 1325
Table 23-2. Signals by Pin Number ..................................................................................... 1326
Table 23-3. Signals by Signal Name ................................................................................... 1333
Table 23-4. Signals by Function, Except for GPIO ............................................................... 1339
Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1346
Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1348
Table 23-7. Connections for Unused Signals (64-Pin LQFP) ................................................. 1351
Table 24-1. Absolute Maximum Ratings .............................................................................. 1353
Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1353
Table 24-3. Temperature Characteristics ............................................................................. 1354
Table 24-4. Thermal Characteristics ................................................................................... 1354
Table 24-5. Recommended DC Operating Conditions .......................................................... 1355
Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1355
Table 24-7. GPIO Current Restrictions ................................................................................ 1355
Table 24-8. GPIO Package Side Assignments ..................................................................... 1356
Table 24-9. JTAG Characteristics ....................................................................................... 1358
Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1360
Table 24-11. Reset Characteristics ....................................................................................... 1365
Table 24-12. LDO Regulator Characteristics ......................................................................... 1367
Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1368
Table 24-14. Actual PLL Frequency ...................................................................................... 1368
Table 24-15. PIOSC Clock Characteristics ............................................................................ 1369
Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1369
Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1369
Table 24-18. Main Oscillator Input Characteristics ................................................................. 1370
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Table 24-19. Crystal Parameters .......................................................................................... 1372
Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1373
Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1373
Table 24-22. System Clock Characteristics with USB Operation ............................................. 1374
Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1375
Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1375
Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1377
Table 24-26. Hibernation Module AC Characteristics ............................................................. 1377
Table 24-27. Flash Memory Characteristics ........................................................................... 1378
Table 24-28. EEPROM Characteristics ................................................................................. 1378
Table 24-29. GPIO Module Characteristics ............................................................................ 1379
Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1380
Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1381
Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1381
Table 24-33. ADC Electrical Characteristics .......................................................................... 1383
Table 24-34. SSI Characteristics .......................................................................................... 1386
Table 24-35. I
2
C Characteristics ........................................................................................... 1389
Table 24-36. Analog Comparator Characteristics ................................................................... 1391
Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1391
Table 24-38. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 0 .......................................................................................................... 1391
Table 24-39. Analog Comparator Voltage Reference Characteristics, V
DDA
= 3.3V, EN= 1, and
RNG = 1 .......................................................................................................... 1392
Table 24-40. Current Consumption ....................................................................................... 1393
Table A-1. Orderable Part Numbers .................................................................................. 1396
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TM4C123GH6PM Microcontroller
List of Registers
The Cortex-M4F Processor ........................................................................................................... 68
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 76
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 76
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 76
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 76
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 76
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 76
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 76
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 76
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 76
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 76
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 76
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 76
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 76
Register 14: Stack Pointer (SP) ........................................................................................................... 77
Register 15: Link Register (LR) ............................................................................................................ 78
Register 16: Program Counter (PC) ..................................................................................................... 79
Register 17: Program Status Register (PSR) ........................................................................................ 80
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 84
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 85
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 86
Register 21: Control Register (CONTROL) ........................................................................................... 87
Register 22: Floating-Point Status Control (FPSC) ................................................................................ 89
Cortex-M4 Peripherals ................................................................................................................. 121
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 137
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 139
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 140
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 141
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 141
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 141
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 141
Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 142
Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 143
Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 143
Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 143
Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 143
Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 144
Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 145
Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 145
Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 145
Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 145
Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 146
Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 147
Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 147
Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 147
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Register 22: Interrupt 96-127 Clear Pending (UNPEND3), offset 0x28C ............................................... 147
Register 23: Interrupt 128-138 Clear Pending (UNPEND4), offset 0x290 .............................................. 148
Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 149
Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 149
Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 149
Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 149
Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 150
Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 151
Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 151
Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 151
Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 151
Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 151
Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 151
Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 151
Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 151
Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 151
Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 151
Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 151
Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 151
Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 151
Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 151
Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 151
Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 151
Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 153
Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 153
Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 153
Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 153
Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 153
Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 153
Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 153
Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 153
Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 153
Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 153
Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 153
Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 153
Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 153
Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 153
Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 153
Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 153
Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 153
Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 153
Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 153
Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 155
Register 65: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 156
Register 66: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 158
Register 67: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 159
Register 68: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 162
Register 69: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 163
19November 15, 2013
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TM4C123GH6PM Microcontroller
Register 70: System Control (SYSCTRL), offset 0xD10 ....................................................................... 165
Register 71: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 167
Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 169
Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 170
Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 171
Register 75: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 172
Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 176
Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 182
Register 78: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 183
Register 79: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 184
Register 80: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 185
Register 81: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 186
Register 82: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 188
Register 83: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 189
Register 84: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 189
Register 85: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 189
Register 86: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 189
Register 87: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 191
Register 88: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 191
Register 89: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 191
Register 90: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 191
Register 91: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 194
Register 92: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 195
Register 93: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 197
Register 94: Floating-Point Default Status Control (FPDSC), offset 0xF3C ........................................... 198
System Control ............................................................................................................................ 211
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 237
Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 239
Register 3: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 242
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 243
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 246
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 248
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 251
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 253
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 257
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 259
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 262
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 263
Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 265
Register 14: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 267
Register 15: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 269
Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 270
Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 271
Register 18: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 272
Register 19: Sleep Power Configuration (SLPPWRCFG), offset 0x188 ................................................. 273
Register 20: Deep-Sleep Power Configuration (DSLPPWRCFG), offset 0x18C ..................................... 275
Register 21: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4 ..................................................... 277
Register 22: LDO Sleep Power Calibration (LDOSPCAL), offset 0x1B8 ................................................ 279
November 15, 201320
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Table of Contents
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