FPGA基础原型设计最佳实践手册

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本资源是一份名为"FPGA-Based Prototyping Methodology Manual"的专业原型验证手册，由Doug Amos（来自Synopsys, Inc.）和来自Xilinx, Inc.的其他作者共同编写。该手册专注于FPGA（Field-Programmable Gate Array）为基础的原型设计最佳实践，为电子工程师和硬件开发人员提供了深入理解和应用FPGA进行系统级原型设计的重要指导。 FPGA原型设计方法论是现代电子工程中的关键工具，它允许设计者在产品上市前快速验证和迭代他们的电路概念。FPGA平台的优势在于其灵活性和可编程性，使得开发者能够在硬件上实现功能原型，从而加快创新速度并降低风险。这份手册覆盖了以下关键知识点： 1. FPGA基础知识：首先介绍了FPGA的基本原理，包括逻辑块、可编程逻辑阵列（PLA）、查找表（LUT）、 Flip-Flops等基本构建单元，以及如何利用FPGA的结构进行逻辑设计。 2. 设计流程：详细描述了从概念设计到实际部署的完整流程，包括需求分析、功能划分、逻辑实现、时序分析、布线策略和资源优化等步骤。 3. 仿真与验证：涵盖了硬件描述语言（如 VHDL或Verilog）的使用，以及针对FPGA的模型验证、静态时序分析、功耗分析等工具和技术的应用。 4. 最佳实践和案例研究：提供了一些成功的设计案例，展示了如何有效地运用FPGA原型验证来解决实际问题，以及避免常见陷阱和错误的方法。 5. 合作与许可：提到了版权信息，强调了未经授权复制或翻译此作品的限制，确保遵循知识产权规定。 6. 工具和技术集成：介绍了Synopsys和Xilinx等公司的相关工具，如Synopsys Design Compiler和Xilinx ISE/IoT SDK，这些工具对于实现高效FPGA原型设计至关重要。通过阅读这份手册，读者能够提升FPGA原型设计的技能，优化设计效率，减少成本，并确保所开发的原型满足性能、功耗和可靠性要求。无论是初学者还是经验丰富的工程师，都能从中获得宝贵的知识和实践经验。

FPGA-Based Prototyping Methodology Manual xiii

3.5.1. Controlling the back-end ..................................................... 75

3.5.2. Additional back-end tools ................................................... 77

3.6. Debugging tools .................................................................................... 77

3.6.1. Design instrumentation for probing and tracing................... 78

3.6.2. Real-time signal probing: test points ................................... 78

3.6.3. Real-time signal probing: non-embedded ............................ 80

3.6.4. Non real-time signal tracing ................................................ 81

3.6.5. Signal tracing at netlist level ............................................... 82

3.6.6. Signal tracing at RTL .......................................................... 85

3.6.7. Summarizing debugging tool options .................................. 89

3.7. Summary............................................................................................... 90

CHAPTER 4

Getting started ...................................................................... 91

4.1. A getting-started checklist ..................................................................... 91

4.2. Estimating the required resources: FPGAs............................................. 92

4.2.1. How mature does the SoC design need to be? ..................... 93

4.2.2. How much of the design should be included?...................... 94

4.2.3. Design blocks that map outside of the FPGA ...................... 95

4.2.4. How big is an FPGA? ......................................................... 97

4.2.5. How big is the whole SoC design in FPGA terms? .............. 99

4.2.6. FPGA resource estimation ................................................ 100

4.2.7. How fast will the prototype run? ....................................... 102

4.3. How many FPGAs can be used in one prototype? ............................... 104

4.4. Estimating required resources.............................................................. 106

4.5. How long will it take to process the design? ........................................ 106

4.5.1. Really, how long will it take to process the design? .......... 108

4.5.2. A note on partitioning runtime .......................................... 109

4.6. How much work will it be? ................................................................. 109

4.6.1. Initial implementation effort ............................................. 110

4.6.2. Subsequent implementation effort ..................................... 111

4.6.3. A note on engineering resources ....................................... 111

4.7. FPGA platform ................................................................................... 112

4.8. Summary............................................................................................. 113

CHAPTER 5

Which platform? (1) build-your-own ................................. 115

5.1. What is the best shape for the platform? .............................................. 115

5.1.1. Size and form factor.......................................................... 115

xiv Table of Contents

5.1.2. Modularity ........................................................................ 117

5.1.3. Interconnect ...................................................................... 119

5.1.4. Flexibility ......................................................................... 121

5.2. Testability ........................................................................................... 122

5.3. On-board clock resources .................................................................... 123

5.3.1. Matching clock delays on and off board ............................ 124

5.3.2. Phase-locked loops (PLL) ................................................. 125

5.3.3. System clock generation ................................................... 126

5.4. Clock control and configuration .......................................................... 128

5.5. On-board Voltage Domains ................................................................. 128

5.6. Power supply and distribution ............................................................. 129

5.6.1. Board-level power distribution .......................................... 131

5.6.2. Power distribution physical design considerations ............. 132

5.7. System reliability management ............................................................ 133

5.7.1. Power supply monitoring .................................................. 133

5.7.2. Temperature monitoring and management ........................ 134

5.7.3. FPGA cooling ................................................................... 136

5.8. FPGA configuration ............................................................................ 137

5.9. Signal integrity .................................................................................... 138

5.10. Global start-up and reset .................................................................... 139

5.11. Robustness ........................................................................................ 139

5.12. Adopting a standard in-house platform .............................................. 140

CHAPTER 6

Which platform? (2) ready-made ....................................... 143

6.1. What do you need the board to do?...................................................... 143

6.2. Choosing the board(s) to meet your goals ............................................ 144

6.3. Flexibility: modularity......................................................................... 146

6.4. Flexibility: interconnect ...................................................................... 147

6.5. What is the ideal interconnect topology? ............................................. 150

6.6. Speed: the effect of interconnect delay ................................................ 153

6.6.1. How important is interconnect flight time? ....................... 156

6.7. Speed: quality of design and layout ..................................................... 157

6.8. On-board support for signal multiplexing ............................................ 158

6.9. Cost and robustness ............................................................................. 159

6.9.1. Supply of FPGAs governs delivery of boards .................... 160

6.10. Capacity ............................................................................................ 160

FPGA-Based Prototyping Methodology Manual xv

6.11. Summary ........................................................................................... 162

CHAPTER 7

Getting the design ready for the prototype ........................ 165

7.1. Why “get the design ready to prototype?” ........................................... 165

7.1.1. RTL modifications for prototyping ................................... 166

7.2. Adapting the design’s top level ........................................................... 167

7.2.1. Handling the IO pads ........................................................ 168

7.2.2. Handling top-level chip support elements ......................... 168

7.3. Clock gating ........................................................................................ 170

7.3.1. Problems of clock gating in FPGA .................................... 171

7.3.2. Converting gated clocks .................................................... 172

7.4. Automatic gated-clock conversion....................................................... 174

7.4.1. Handling non-convertible gating logic .............................. 176

7.4.2. Clock gating summary ...................................................... 179

7.5. Selecting a subset of the design for prototyping ................................... 180

7.5.1. SoC block removal and its effect....................................... 180

7.5.2. SoC element tie-off with stubs .......................................... 183

7.5.3. Minimizing and localizing RTL changes ........................... 184

7.5.4. SoC element replacement with equivalent RTL................. 186

7.5.5. SoC element replacement by inference ............................. 189

7.5.6. SoC element replacement by instantiation ......................... 191

7.5.7. Controlling inference using directives ............................... 193

7.6. Handling RAMs .................................................................................. 194

7.7. Handling instantiated SoC RAM in FPGA .......................................... 195

7.7.1. Note: RAMs in Virtex

-6 FPGAs ..................................... 195

7.7.2. Using memory wrappers ................................................... 197

7.7.3. Advanced self-checking wrappers ..................................... 204

7.8. Implementing more complex RAMs .................................................... 207

7.8.1. Example: implementing multiport RAMs.......................... 207

7.8.2. Example: bit-enabled RAMs ............................................. 209

7.8.3. NOTE: using BlockRAM as ROMs .................................. 212

7.9. Design implementation: synthesis ....................................................... 212

7.9.1. Note: using existing constraints for the SoC design ........... 213

7.9.2. Tuning constraints ............................................................ 215

7.10. Prototyping power-saving features .................................................... 215

7.11. Design implementation: place & route ............................................... 216

xvi Table of Contents

7.12. Revision control during prototyping .................................................. 218

7.13. Summary ........................................................................................... 219

CHAPTER 8

Partitioning and reconnecting ............................................ 221

8.1. Do we always need to partition across FPGAs? ................................... 221

8.1.1. Do we always need EDA partitioning tools? ..................... 222

8.2. General partitioning overview ............................................................. 222

8.2.1. Recommended approach to partitioning ............................ 223

8.2.2. Describing board resources to the partitioner .................... 224

8.2.3. Estimate area of each sub-block ........................................ 225

8.2.4. Assign SoC top-level IO ................................................... 226

8.2.5. Assign highly connected blocks ........................................ 227

8.2.6. Assign largest blocks ........................................................ 229

8.2.7. Assign remaining blocks ................................................... 231

8.2.8. Replicate blocks to save IO ............................................... 231

8.2.9. Multiplex excessive FPGA interconnect ........................... 234

8.2.10. Assign traces................................................................... 234

8.2.11. Iterate partitioning to improve speed and fit .................... 237

8.3. Automated partitioning........................................................................ 239

8.4. Improving prototype performance ....................................................... 240

8.4.1. Time budgeting at sequential boundaries .......................... 241

8.4.2. Time budgeting at combinatorial boundaries ..................... 242

8.5. Design synchronization across multiple FPGAs .................................. 244

8.5.1. Multi-FPGA clock synchronization ................................... 244

8.5.2. Multi-FPGA reset synchronization .................................... 247

8.5.3. Multi FPGA start-up synchronization ............................... 250

8.6. More about multiplexing ..................................................................... 251

8.6.1. What do we need for inter-FPGA multiplexing? ............... 251

8.7. Multiplexing schemes ......................................................................... 253

8.7.1. Schemes based on multiplexer .......................................... 253

8.7.2. Note: qualification criteria for multiplexing nets ............... 254

8.7.3. Schemes based on shift-registers ....................................... 255

8.7.4. Worked example of multiplexing ...................................... 256

8.7.5. Scheme based on LVDS and IOSERDES.......................... 262

8.7.6. Which multiplexing scheme is best for our design? ........... 264

8.8. Timing constraints for multiplexing schemes ...................................... 265

FPGA-Based Prototyping Methodology Manual xvii

8.9. Partitioning and reconnection: summary .............................................. 266

CHAPTER 9

Design-for-Prototyping ....................................................... 267

9.1. What is Design-for-Prototyping? ......................................................... 267

9.1.1. What’s good for FPGA is usually good for SoC ................ 268

9.2. Procedural guidelines .......................................................................... 268

9.2.1. Integrate RTL team and prototypers .................................. 269

9.2.2. Define list of deliverables for prototyping team ................ 270

9.2.3. Prototypers work with software team ................................ 272

9.3. Integrate the prototype with the verification plan ................................. 272

9.3.2. Documentation well and use revision control .................... 274

9.3.3. Adopt company-wide standard for hardware ..................... 274

9.3.4. Include Design-for-Prototyping in RTL standards ............. 274

9.4. Design guidelines ................................................................................ 275

9.4.1. Follow modular design principles ..................................... 277

9.4.2. Pre-empt RTL changes with ‘define and macros ............... 278

9.4.3. Avoid latches .................................................................... 279

9.4.4. Avoid long combinatorial paths ........................................ 279

9.4.5. Avoid combinatorial loops ................................................ 280

9.4.6. Provide facility to override FFs with constants .................. 280

9.5. Guidelines for isolating target specificity ............................................ 281

9.5.1. Write pure RTL code ........................................................ 281

9.5.2. Make source changes as low-impact as possible ................ 281

9.5.3. Maintain memory compatibility ........................................ 282

9.5.4. Isolation of RAM and other macros .................................. 282

9.5.5. Use only IP that has an FPGA version or test chip ............ 284

9.6. Clocking and architectural guidelines .................................................. 284

9.6.1. Keep clock logic in its own top-level block ....................... 285

9.6.2. Simplify clock networks for FPGA ................................... 285

9.6.3. Design synchronously ....................................................... 286

9.6.4. Synchronize resets ............................................................ 286

9.6.5. Synchronize block boundaries........................................... 286

9.6.6. Think how the design might run if clocked slowly ............ 287

9.6.7. Enable bottom-up design flows ......................................... 287

9.7. Summary............................................................................................. 288

CHAPTER 10 IP and high-speed interfaces ............................................... 289

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