ARM Cortex M3 汇编语言编程入门指南

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"ARM Cortex M3 汇编语言编程（英文版）" 这本书详细介绍了针对ARM Cortex-M3处理器的汇编语言编程技术。ARM Cortex-M3是ARM公司设计的一款高效、低功耗的微控制器核心，广泛应用于嵌入式系统。汇编语言编程对于理解处理器的工作原理、优化代码性能以及在资源受限的环境中开发软件至关重要。作者Vincent Mahout通过这本书，引导读者深入学习Cortex-M3架构和汇编语言编程。书中涵盖了以下关键知识点： 1. **ARM架构基础**：介绍ARM Cortex-M3处理器的基本结构，包括寄存器布局、指令集架构（ISA）、中断处理机制以及内存模型。 2. **汇编语法**：详细讲解ARM汇编语言的基本语法，包括指令、寻址模式、操作符和伪指令，帮助读者编写有效的汇编代码。 3. **程序流程控制**：涵盖分支、循环和跳转指令，这些都是编写复杂程序的基础。 4. **中断和异常处理**：讨论Cortex-M3中的中断和异常处理机制，包括中断向量表和中断服务例程的编写。 5. **内存管理**：讲解如何访问和操作内存，包括堆栈操作、数据存储和加载指令。 6. **调试技巧**：介绍使用汇编语言进行调试的方法，包括使用调试器和查看内存和寄存器状态。 7. **性能优化**：讨论如何通过优化汇编代码来提高程序运行速度和降低资源消耗，这对于嵌入式系统尤其重要。 8. **与高级语言结合**：阐述如何将汇编语言代码与C或C++等高级语言混合编程，实现性能敏感部分的优化。 9. **实例分析**：提供实际的示例代码，帮助读者理解并应用所学知识，解决具体问题。 10. **工具和环境**：介绍常用的开发工具，如IDE、编译器和模拟器，以及如何设置开发环境。本书适合对嵌入式系统和微控制器感兴趣的开发者，尤其是那些希望深入了解ARM Cortex-M3并使用汇编语言进行优化编程的工程师。通过阅读，读者将能够编写高效的汇编代码，并在实际项目中运用这些技能。虽然内容为英文，但200多页的篇幅使得它相对易于阅读和理解，对于有基础的读者来说是一本有价值的参考资料。

4 Assembly Language Programming

logical unit for the proper execution of different instructions. The functioning of this

block will be explained in detail in Chapter 2. It is necessary to understand its

mechanism in order to write programs in assembly language.

– Nested Vector Interrupt Controller (NVIC): Cortex-M3 is intended to be

embedded in a μcontroller, which includes peripheral units to allow interfacing with

the outside world. These units can be seen as independent micromachines. The

exchanges between them and Cortex-M3 must consequently be rhythmic and

organized so that the sequence of tasks complies with rules (the concept of

priorities) and determinism set in advance by the programmer. NVIC plays the role

of “director”. It is in charge of receiving, sorting and distributing the different

interrupt requests generated by the collection of μcontroller units. It also manages

events that threaten the smooth running of the code being executed (reset, memory

bus problem, division by 0, etc.).

Figure 1.1. Cortex-M3 functional diagram

– Memory Protection Unit (MPU): This block is optional – a designer using

Cortex-M3 to make their μcontroller can choose not to implement this function. This

block allows the allocation of specific read and/or write privileges to specific

memory zones. In this way, when different independent software tasks are executed

in parallel (or more precisely in sharing the common resources of the processor), it

is possible to allocate a memory zone to each task that is inaccessible to the other

tasks. This mechanism therefore allows programmer to secure memory access. It

Overview of Cortex-M3 Architecture 5

usually goes hand-in-hand with the use of an operating system (real-time or

otherwise) for the software layer.

– Bus matrix: This unit is a kind of gigantic intelligent multiplex. It allows

connections to the external buses:

- the ICode bus (32-bit AHB-Lite type

) that carries the memory mappings

allocated to the code and instructions;

- the DCode bus (also 32-bit AHB-Lite type) that is responsible for

reading/writing in data memory zones;

- the System bus (again 32-bit AHB-Lite type), which deals with all system

space access;

- the Private Peripheral Bus (PPB): all peripherals contained in the μcontroller

are added to the Cortex-M3 architecture by the designer. ARM designed a specific

bus to allow exchanges with peripherals. This bus contains 32 bits, but in this case it

is the Advanced Peripheral Bus (APB) type. This corresponds to another bus

protocol (which you may know is less efficient than AHB type, but it is more than

sufficient for access to peripheral units). It should be noted that the bus matrix plays

an important role in transmitting useful information to development units, which are

mentioned in the next section.

1.2.1.2. Development units

The development of programs is an important and particularly time-consuming

step in the development cycle of an embedded application. What is more, if the

project has certification imperatives, it is necessary that tools (software and/or

material) allowing maximum monitoring of the events occurring in each clock cycle

are at its disposition. In Cortex-M3, the different units briefly introduced below

correspond to these monitoring functions. They are directly implanted in the silicon

of the circuit, which allows them to use these development tools at a material level.

An external software layer is necessary, however, to recover and process the

information issued by these units. The generic idea behind the introduction of

hardware solutions is to offer the programmer the ability to test and improve the

reliability of (or certify) his or her code without making any changes. It is

convenient (and usual) to insert some print (“Hello I was here”) into a software

structure to check that the execution passes through this structure. This done, a code

modification is introduced, which can modify the global behavior of the program.

This is particularly true when time management is critical for the system, which, for

2 Advanced High-performance Bus (AHB) is a microcontroller bus protocol brought in by

ARM.

6 Assembly Language Programming

embedded systems controlled by a μcontroller, is almost always the case. The units

relating to monitoring functions in Cortex-M3 include:

– Flash Patch and Breakpoint (FPB): the FPB is the most basic function for this

process. It is linked to the concept of a stopping point (breakpoint), which imposes a

stop on a line of code (that is to say, an instruction in the case of assembly language)

located beforehand. This unit is used to mark instructions so that when they come

into effect, the processor puts itself into a particular mode of operation: debug mode.

Development software (and other pieces of software that use it) can therefore

observe the state of the processor and directly influence the running of the program

in progress.

– Data Watchpoint and Trace (DWT): the concept of a “point of observation” is

the counterpart to the concept of a stopping point for the data. The DWT stops the

program running when it works on marked data rather than a marked instruction.

This action can be in reading, writing, passing on values, etc. The unit can also send

requests to the ITM and ETM units.

– Embedded Trace Macrocell (ETM): the concept of trace includes the capacity

for the hardware to record a sequence of events during program execution. The

recovery of these recordings allows the programmer to analyze the running of the

program, whether good or bad. In the case of ETM, only information on instructions

is stored in a first in, first out (FIFO)-type structure. As with the MPU unit, this unit

is optional.

– Instrumentation Trace Macrocell (ITM): this unit also allows the collection of

trace information on applications (software, hardware or time). The information is

more limited than with the ETM unit but is nevertheless very useful in isolating a

vicious bug. This is especially true if the optional ETM is not present.

– Advanced High-performance Bus Access Port (AHB-AP): this is an

(Input/Output) port within Cortex-M3 that is designed to debug. It allows access to

all records and all addressable memory space. It has priority in the arbitration

policies of the bus matrix. This unit is connected upstream by the Serial Wire JTAG

(Joint Test Action Group) port (SW/JTAG), which is the interface (with its physical

layers) that connects to the outside world, equipped with its part of the JTAG probe.

The JTAG protocol is a standardized protocol used by almost all semiconductor

manufacturers.

– Trace Port Interface Unit (TPUI): the TPUI plays the same role in trace

functions as the SW/JTAG plays in debug functions. Its existence is principally

linked to the fact that it is necessary to sort the external world recordings collected

by the ITM. There is an additional challenge, however, when an ETM unit is

present, as it must also manage the data stored there. Its secondary role is

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