"TI-DS110DF1610.pdf：以太网重定时器技术手册"

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SMBus

REFCLK_IN

IN+

IN-

Retimer/CDR

Driver

OUT+

OUT-

VCO

100:

100

VGA/DFE

Regulator

Digital Core

1.2V

Regulator

FIR Filter

Signal

Detect

Cross Point

2.5V

Eye

Opening

Monitor

PRBS

Check

Patt.

Gen

DS110DF1610

www.ti.com

SNLS472A –JANUARY 2014–REVISED JUNE 2017

Product Folder Links: DS110DF1610

Functional Block Diagrams (continued)

Figure 2. DS110DF1610 Simplified Data Path Diagram

6.3 Feature Description

6.3.1 Device Data Path Operation

The DS110DF1610 data path consists of several key blocks as shown in Figure 2. These key circuits are:

• AC-coupled Receiver with Signal Detect

• CTLE

• Cross Point Switch

• DFE with VGA

• CDR

• Differential Driver with FIR Filter

6.3.1.1 AC-Coupled Receiver With Signal Detect

The differential receiver for each DS110DF1610 channel contains on chip AC coupling capacitors. The minimum

bandwidth for this AC coupled receiver is 16kHz. The receiver also contains a signal detect circuit.

The signal detect circuit monitors the energy level on the receiver inputs and powers on or off the rest of the high

speed data path if a signal is detected or not. By default, each channel allows the signal detect circuit to

automatically power on or off the rest of the high speed data path depending on if a signal is present. Users can

obtain manual control over the signal detect block through the SMBus channel registers. This can be useful if it is

desired manually force channels to be disabled. For information on how to manually operate the signal detect

circuit please see the DS110DF1610 Programming Guide and channel register 0x15 information.

6.3.1.2 CTLE

The CTLE in the DS110DF1610 is a fully adaptive equalizer with adjustable bandwidth and optional limiting

stage. The CTLE is adapted to a boost setting according to a Figure of Merit (FOM) during the lock acquisition

process. Once the CDR has locked, the CTLE boost level will be frozen until a manual re-adapt command is

issued or until the CDR re-enters the lock acquisition state.

DS110DF1610

SNLS472A –JANUARY 2014–REVISED JUNE 2017

www.ti.com

Product Folder Links: DS110DF1610

Feature Description (continued)

The CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-

boost combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost

combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel

registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost

settings. Users also have the option of limiting the EQ table length to any value between a minimum value of 1

and a maximum value of 32.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost

combinations that sum to the same number will have approximately the same boost level, but will result in a

different shape for the EQ transfer function (boost curve). The boost levels can be set between 6 dB and 38 dB.

The CTLE bandwidth can be adjusted through SMBus control to 3 different levels:

CTLE BANDWIDTH SETTING RESULTING BANDWIDTH (GHz)

Full Rate 9

Mid Rate 7

Half Rate 5

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather

than a linear stage. This is useful in some applications, but it should not be typically used in combination with the

DFE.

6.3.1.3 Cross Point Switch

Each quad has a 4x4 non-blocking analog cross point switch. This allows for full switching or broadcasting of

data between any input within the quad to any output within the quad. Since the cross point switch is an analog

implementation, all of the channels are allowed to operate asynchronously. The analog implementation also

minimizes added latency through the device.

As shown in Figure 1, the cross point switch connections for each quad are located between CTLE and DFE in

each channel.

The cross point switch consists of consists of 4 sets of MUXs and buffers. In each channel there is a local buffer

and a multi-drive buffer. The local buffer transmits data from the CTLE to the DFE of the same channel. The

multi drive buffer transmits data from the CTLE to the DFE(s) of other channels within the quad. Each channel

has two MUXs:

1. Data path mux – Selects whether to get data from the local buffer or from other channel’s multi-driver buffer

2. Control bus mux – Selects where the signal detect and EQ control bus should be connected. This setting

should mirror the data path mux setting. Note, when an EQ is connected to another channel’s CDR the EQ

becomes associated with that CDR’s register set. For example, if the cross point was configured to do point

to point switching from the inputs of channel 0 to the output of channel 1 and the inputs of channel 1 to the

outputs of channel 0, the EQ physically located at the pins for inputs of channel 0 would be accessible

through the register set of channel 1.

A simplified diagram of the cross point switch is shown in Figure 3.

DS110DF1610

SNLS472A –JANUARY 2014–REVISED JUNE 2017

www.ti.com

Product Folder Links: DS110DF1610

• 1:4 – any channel input to all 4 channels output

When the cross point switch is configured to replicate/broadcast data a master must be assigned during the

cross point configuration. The master channel will have control over the CTLE adaption. All of the slave channels

will be able to adapt their own DFE, but will not have control to adapt the CTLE. In this type of configuration there

must be 1 channel assigned as a master. All other channels in the broadcast network must be assigned as

slaves. There cannot be more than one master channel in a broadcast network.

In a typical data replication/broadcast application users must configure the following for each channel:

1. Control bus mux setting (ch reg 0x9B)

2. Data path mux setting (ch reg 0x96)

3. Enabling/Disabling the local or multi-drive buffers for each channel (ch reg 0x96)

4. Master/Slave assignment (ch reg 0x96)

5. Cross point enable bit (ch reg 0x96)

6. Perform a CDR reset and reset release (ch reg 0x0A)

6.3.1.4 DFE With VGA

A 5-tap DFE with a VGA can be enabled within the data path of each channel to assist with reducing the effects

of cross talk, reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled,

regardless of the selected adapt mode. Once the DFE has been enabled it can be configured to adapt only

during lock acquisition or to adapt continuously. The DFE can also be manually configured to specified tap

polarities and tap weights. However, when the DFE is configured manually the DFE auto-adaption should be

disabled.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

DFE PARAMETER VALUE (mV)

Tap 1 Weight Range 0 – 224

Tap 2-5 Weight Range 0 – 112

Tap Weight Step Size 7

A VGA is located at the input to the DFE block. The VGA has 2-bit control to allow for 4 levels of boost. The VGA

can be used to assist in the recovery of extremely small signals. Note that the VGA is integrated within the DFE,

so in order to use the VGA the DFE must be enabled.

6.3.1.5 Clock and Data Recovery

The CDR block consists of a Phase Locked Loop (PLL), reference clock based PPM counter, Input and Output

Data Multiplexers (mux) and circuits to monitor single bit transitions and detect false locking. The CDR sampling

position is fixed at the 0.5UI location for each bit.

By default, the equalized data is fed into the CDR for clock and data recovery. This data is then output to FIR

filter and differential driver. Users can configure the CDR data to route the recovered clock and data to the PRBS

checker. Users also have the option of configuring the output of the CDR to send raw non-retimed data, or data

from the pattern generator.

The CDR requires the following in order to be properly configured:

• Input reference clock with proper reference clock divider setting to run the PPM counter.

• Expected data rates must be programmed into the CDR either through the rate/sub-rate table or entered

manually with the corrected divider settings.

6.3.1.6 Reference Clock

The reference clock is not part of the CDR’s PLL. The reference clock is connected only to the PPM counter for

each CDR. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed

values in the rate/sub-rate table or the manually entered data rates.

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