F1C600芯片使用手册：编程与寄存器详解

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"F1C600用户手册，包含了全志科技F1C600芯片的使用指南，包括寄存器配置等编程细节。" 本文档是全志科技（Allwinner Technology）对于F1C600芯片的用户手册，版本1.0，发布于2015年11月10日。全志科技保留所有版权，并声明该文档为原创作品，未经其书面许可，任何部分的复制都需要明确承认版权所有者。手册中的声明部分指出，此文档中的信息被认为是准确且可靠的，但全志科技保留随时对电路设计和/或规格进行更改而不事先通知的权利。使用者自行承担使用该芯片可能导致的任何侵犯第三方专利或其他权利的责任，全志科技不对此提供任何形式的担保。同时，该文档并不直接或间接授予任何全志科技的专利或专利权许可。文档中提到的解决方案可能需要第三方许可。 F1C600芯片的用户手册详细阐述了如何正确使用和编程这款芯片，特别是寄存器的配置，这是嵌入式系统设计中的关键部分。寄存器是微处理器内部与外部硬件交互的重要接口，用于存储和控制芯片的运行状态。了解和正确配置寄存器设置对于优化性能、管理电源消耗以及实现特定功能至关重要。手册通常会包含以下内容： 1. 芯片概述：介绍F1C600芯片的基本特性和功能。 2. 硬件接口：描述芯片的引脚定义、I/O接口、总线接口等。 3. 寄存器描述：列出所有可编程寄存器，解释它们的作用和默认值。 4. 控制和状态寄存器：详述如何通过这些寄存器来监控和控制芯片的工作状态。 5. 系统时钟和电源管理：指导如何配置时钟频率和电源模式以达到最佳能效。 6. 内存管理：涉及内存映射、缓存策略等。 7. 中断和异常处理：说明中断源及其处理机制。 8. 应用示例：提供实际应用中的配置示例，帮助开发者快速上手。开发者在使用F1C600芯片进行产品开发时，必须参照该手册，理解并遵循其中的指南，以确保系统能够正确、高效地运行。同时，考虑到可能需要的第三方许可，开发者还需要关注相关的知识产权问题，确保合法合规使用。

Revision History

4.2.5. Operation Mode ...................................................................................................................................... 146

4.2.5.1. Basic principle .............................................................................................................................. 146

4.2.5.2. Single-ended mode ...................................................................................................................... 146

4.2.5.3. Differential mode ......................................................................................................................... 147

4.2.5.4. Single touch detection ................................................................................................................. 147

4.2.5.5. Dual touch detection .................................................................................................................... 148

4.2.5.6. Touch pressure measurement ...................................................................................................... 148

4.2.5.7. Pen down detection, with programmable sensitivity .................................................................. 149

4.2.5.8. Median and averaging filter ......................................................................................................... 150

4.2.6. TP Register List ........................................................................................................................................ 151

4.2.7. TP Register Description ........................................................................................................................... 151

4.2.7.1. TP Control Register 0 .................................................................................................................... 151

4.2.7.2. TP Control Register 1 .................................................................................................................... 152

4.2.7.3. TP Control Register 2 .................................................................................................................... 153

4.2.7.4. TP Control Register 3

.................................................................................................................... 154

4.2.7.5. TP Interrupt FIFO Control Register ............................................................................................... 154

4.2.7.6. TP Interrupt FIFO Status Register ................................................................................................. 155

4.2.7.7. TP Common Data Register ............................................................................................................ 156

4.2.7.8. TP Data Register ........................................................................................................................... 156

4.3. Audio Codec ....................................................................................................................................................... 157

4.3.1. Overview ................................................................................................................................................. 157

4.3.2. Feature .................................................................................................................................................... 157

4.3.3. Block diagram .......................................................................................................................................... 157

4.3.4. Signal Description .................................................................................................................................... 157

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Revision History

4.3.5. Power Description ................................................................................................................................... 158

4.3.6. Function Description ............................................................................................................................... 158

4.3.6.1. ADC ............................................................................................................................................... 158

4.3.6.2. Stereo ADC ................................................................................................................................... 158

4.3.6.3. Mixer ............................................................................................................................................ 158

4.3.6.4. Headphone Mixer ......................................................................................................................... 158

4.3.6.5. ADC Record Mixer ........................................................................................................................ 158

4.3.6.6. Analog Audio Input Path .............................................................................................................. 159

4.3.6.7. FM Input ....................................................................................................................................... 159

4.3.7. Audio Codec Register List ........................................................................................................................ 160

4.3.8. Audio Codec Register Description ........................................................................................................... 160

4.3.8.1. DAC Digital Part Control Register ................................................................................................. 160

4.3.8.2. DAC FIFO Control Register ............................................................................................................ 162

4.3.8.3. DAC FIFO Status Register .............................................................................................................. 164

4.3.8.4. DAC TX DATA Register ................................................................................................................... 164

4.3.8.5. ADC FIFO Control Register ............................................................................................................ 165

4.3.8.6. ADC FIFO Status Register .............................................................................................................. 166

4.3.8.7. ADC RX DATA Register .................................................................................................................. 167

4.3.8.8. DAC Analog & Output MIXER Control Register ............................................................................ 167

4.3.8.9. ADC Analog and Input mixer Control Register ............................................................................. 169

4.3.8.10. ADC&DAC performance tuning Register .................................................................................... 170

4.3.8.11. Bias & DA16 Calibration Control Register 0 ................................................................................ 171

4.3.8.12. Bias & DA16 Calibration Control Register 1 ................................................................................ 172

4.3.8.13. DAC TX Counter Register ............................................................................................................ 172

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Revision History

4.3.8.14. ADC RX Counter Register ............................................................................................................ 172

4.3.8.15. DAC Debug Register ................................................................................................................... 172

4.3.8.16. ADC Debug Register ................................................................................................................... 173

4.3.8.17. ADC DAP Control Register .......................................................................................................... 173

4.3.8.18. ADC DAP Left Control Register ................................................................................................... 174

4.3.8.19. ADC DAP Right Control Register ................................................................................................. 175

4.3.8.20. ADC DAP Parameter Register ..................................................................................................... 176

4.3.8.21. ADC DAP Left Average Coef Register .......................................................................................... 177

4.3.8.22. ADC DAP Left Decay & Attack Time Register .............................................................................. 177

4.3.8.23. ADC DAP Right Average Coef Register ........................................................................................ 177

4.3.8.24. ADC DAP Right Decay & Attack Time Register ........................................................................... 178

4.3.8.25. ADC DAP HPF Coef Register ........................................................................................................ 178

4.3.8.26. ADC DAP Left Input Signal Low Average Coef Register ................................

.............................. 178

4.3.8.27. ADC DAP Right Input Signal Low Average Coef Register ............................................................ 178

4.3.8.28. ADC DAP Optimum Register ....................................................................................................... 179

Chapter 5. Display ............................................................................................................................................................. 180

5.1. TCON .................................................................................................................................................................. 181

5.1.1. Overview ................................................................................................................................................. 181

5.1.2. Feature .................................................................................................................................................... 181

5.1.3. Block Diagram ......................................................................................................................................... 181

5.1.3.1. LCD Timing Controller .................................................................................................................. 181

5.1.4. TCON Register List ................................................................................................................................... 182

5.1.5. TCON Register Description ...................................................................................................................... 183

5.1.5.1. TCON Control Register .................................................................................................................. 183

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Revision History

5.1.5.2. TCON Interrupt Register 0 ............................................................................................................ 183

5.1.5.3. TCON Interrupt Register 1 ............................................................................................................ 184

5.1.5.4. TCON FRM Control Register ......................................................................................................... 184

5.1.5.5. TCON FRM Seed0 Red Register .................................................................................................... 184

5.1.5.6. TCON FRM Seed0 Green Register ................................................................................................. 184

5.1.5.7. TCON FRM Seed0 Blue Register ................................................................................................... 185

5.1.5.8. TCON FRM Seed1 Red Register .................................................................................................... 185

5.1.5.9. TCON FRM Seed1 Green Register ................................................................................................. 185

5.1.5.10. TCON FRM Seed1 Blue Register ................................................................................................. 185

5.1.5.11. TCON FRM Table Register 0 ........................................................................................................ 185

5.1.5.12. TCON FRM Table Register 1 ........................................................................................................ 185

5.1.5.13. TCON FRM Table Register 2 ........................................................................................................

186

5.1.5.14. TCON FRM Table Register 3 ........................................................................................................ 186

5.1.5.15. TCON0 Control Register .............................................................................................................. 186

5.1.5.16. TCON Clock Control Register ...................................................................................................... 187

5.1.5.17. TCON0 Basic Timing Register 0 .................................................................................................. 187

5.1.5.18. TCON0 Basic Timing Register 1 .................................................................................................. 187

5.1.5.19. TCON0 Basic Timing Register 2 .................................................................................................. 188

5.1.5.20. TCON0 Basic Timing Register 3 .................................................................................................. 188

5.1.5.21. TCON0 HV Timing Register ......................................................................................................... 188

5.1.5.22. TCON0 CPU Interface Control Register ....................................................................................... 189

5.1.5.23. TCON0 CPU Write Register ......................................................................................................... 190

5.1.5.24. TCON0 CPU Read Register .......................................................................................................... 190

5.1.5.25. TCON0 CPU Read NX Register

.................................................................................................... 190

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Revision History

5.1.5.26. TCON0 IO Control Register 0 ...................................................................................................... 190

5.1.5.27. TCON0 IO Control Register 1 ...................................................................................................... 191

5.1.5.28. TCON1 Control Register .............................................................................................................. 191

5.1.5.29. TCON1 Basic Timing Register 0 .................................................................................................. 192

5.1.5.30. TCON1 Basic Timing Register 1 .................................................................................................. 192

5.1.5.31. TCON1 Basic Timing Register 2 .................................................................................................. 192

5.1.5.32. TCON1 Basic Timing Register 3 .................................................................................................. 193

5.1.5.33. TCON1 Basic Timing Register 4 .................................................................................................. 193

5.1.5.34. TCON1 Basic Timing Register 5 .................................................................................................. 193

5.1.5.35. TCON1 IO Control Register 0 ...................................................................................................... 193

5.1.5.36. TCON1 IO Control Register 1 ...................................................................................................... 194

5.1.5.37. TCON Debug Information Register ............................................................................................. 194

5.2. Display Engine Front-End ................................................................................................................................... 196

5.2.1. Overview ................................................................................................................................................. 196

5.2.2. Feature .................................................................................................................................................... 196

5.2.3. Block Diagram ......................................................................................................................................... 196

5.2.4. DEFE Register List .................................................................................................................................... 196

5.2.5. DEFE Register Description ....................................................................................................................... 198

5.2.5.1. DEFE Module Enable Register ...................................................................................................... 198

5.2.5.2. DEFE Frame Process Control Register .......................................................................................... 198

5.2.5.3. DEFE CSC Bypass Register ............................................................................................................. 199

5.2.5.4. DEFE Algorithm Selection Register ............................................................................................... 200

5.2.5.5. DEFE Line Interrupt Conrtol Register............................................................................................ 200

5.2.5.6. DEFE Input Channel 0 Buffer Address Register ............................................................................ 200

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