DP83849ID PHYTER：双端口工业级以太网物理层收发器

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"DP83849ID PHYTER是一款由National Semiconductor Corporation生产的双端口10/100Mb/s以太网物理层收发器，适用于工业温度环境，并支持光纤连接。" DP83849ID PHYTER是National Semiconductor Corporation（现已被Texas Instruments收购）设计的一款工业级以太网物理层收发器，专门用于需要高可靠性和冗余功能的场合，如无线远程基站和工业网络。这款芯片的特点在于提供了两个完全独立的10/100Mb/s以太网端口，能够满足多端口应用的需求。在工业环境中，DP83849ID的设计考虑了恶劣的工作条件，能够承受工业温度范围，确保在极端温度下仍能稳定工作，增强了系统的耐受性和可靠性。此外，由于支持光纤连接，它能够在长距离传输数据时保持信号的完整性，避免了电磁干扰（EMI）的问题，这对于工厂自动化、远程监控和其他对数据安全和传输距离有要求的系统来说至关重要。该器件的核心功能包括： 1. **双端口10/100Mb/s以太网**：每个端口都能独立运行在10Mbps或100Mbps的速度上，提供全双工或半双工模式，满足不同网络速度和配置需求。 2. **光纤支持**（FX）：通过光纤接口实现长距离通信，提高系统的抗干扰能力，适合于需要远距离、高带宽和低延迟的网络环境。 3. **工业温度范围**：能够在-40°C至85°C的温度范围内正常工作，适应各种苛刻的工业环境。 4. **高可靠性**：设计包含错误检测和纠正机制，如CRC校验，确保数据传输的准确性。 5. **系统管理**：可能包含高级网络管理特性，如SNMP（简单网络管理协议），方便网络监控和故障排查。 6. **电源管理**：可能具有低功耗特性，有利于节能和延长设备寿命。 DP83849ID PHYTER的使用可以简化系统设计，因为它集成了必要的物理层功能，减少了外部组件的需求，从而降低了成本和复杂性。同时，其紧凑的封装设计使得它易于集成到各种硬件平台中，为设计工程师提供了极大的便利。 DP83849ID PHYTER是工业网络应用的理想选择，它结合了高性能、高可靠性与灵活的连接选项，为实现可靠的双端口以太网连接提供了强大支持。在设计需要冗余和高稳定性网络连接的系统时，这款芯片是一个值得考虑的关键组件。

15 www.national.com

DP83849ID

1.8 10 Mb/s and 100 Mb/s PMD Interface

1.9 Special Connections

1.10 Power Supply Pins

Signal Name Type Pin # Description

TPTDM_A/FXTDM_A

TPTDP_A/FXTDP_A

TPTDM_B/FXTDM_B

TPTDP_B/FXTDP_B

I/O 26

10BASE-T or 100BASE-TX or 100BASE-FX Transmit Data

In 10BASE-T or 100BASE-TX: Differential common driver trans-

mit output (PMD Output Pair). These differential outputs are auto-

matically configured to either 10BASE-T or 100BASE-TX

signaling.

In Auto-MDIX mode of operation, this pair can be used as the Re-

ceive Input pair.

In 100BASE-FX mode, this pair becomes the 100BASE-FX

Transmit pair.

These pins require 3.3V bias for operation.

TPRDM_A/FXRDM_A

TPRDP_A/FXRDP_A

TPRDM_B/FXRDM_B

TPRDP_B/FXRDP_B

I/O 23

10BASE-T or 100BASE-TX or 100BASE-FX Receive Data

In 10BASE-T or 100BASE-TX: Differential receive input (PMD In-

put Pair). These differential inputs are automatically configured to

accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the

Transmit Output pair.

In 100BASE-FX mode, this pair becomes the 100BASE-FX

Receive pair.

These pins require 3.3V bias for operation.

FXSD_A

(LED_SPEED_A/AN1_A)

FXSD_B

(LED_SPEED_B/AN1_B)

I 20

FX Signal Detect: This pin provides the Signal Detect input for

100BASE-FX mode.

Signal Name Type Pin # Description

RBIAS I 32 Bias Resistor Connection. A 4.87 kΩ 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT O 31 Power Feedback Output. Parallel caps, 10µ F and 0.1µF, s ho ul d

be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin

13), PFBIN2 (pin 27), PFBIN3 (pin35), PFBIN4 (pin 49). See

Section 5.5 for proper placement pin.

PFBIN1

PFBIN2

PFBIN3

PFBIN4

I 7

Power Feedback Input. These pins are fed with power from

PFBOUT pin. A small capacitor of 0.1µF should be connected

close to each pin.

Note: Do not supply power to these pins other than from

PFBOUT.

Signal Name Pin # Description

IOVDD1, IOVDD2, IOVDD3,

IOVDD4

11,51,65,78 I/O 3.3V Supply

IOGND1, IOGND2,

IOGND3, IOGND4

10,52,64,77 I/O Ground

COREGND1, COREGND2 6,55 Core Ground

CDGND1, CDGND2 25,37 CD Ground

ANA33VDD 30 Analog 3.3V Supply

ANAGND1, ANAGND2,

ANAGND3, ANAGND4

22,29,33,40 Analog Ground

17 www.national.com

DP83849ID

2.0 Configuration

This section includes information on the various configura-

tion options available with the DP83849ID. The configura-

tion options described below include:

— Media Configuration

— Auto-Negotiation

— PHY Address and LEDs

— Half Duplex vs. Full Duplex

— Isolate mode

— Loopback mode

—BIST

2.1 Media Configuration

The DP83849ID supports both Twister Pair (100BASE-TX

and 10BASE-T) and Fiber (100BASE-FX) media. Each

port may be independently configured for Twisted Pair (TP)

or Fiber (FX) operation by strap option or by register

access.

At power-up/reset, the state of the COL_A and COL_B pins

will select the media for ports A and B respectively. The

default selection is TP mode, while an external pull-up will

select FX mode of operation. Strapping a port into FX

mode also automatically sets the Far-End Fault Enable, bit

3 of PCSR (16h), the Scramble Bypass, bit 1 of PCSR

(16h) and the Descrambler Bypass, bit 0 of PCSR (16h). In

addition, the media selection may be controlled by writing

to bit 6, FX_EN, of PCSR (16h).

2.2 Auto-Negotiation

The Auto-Negotiation function provides a mechanism for

exchanging configuration information between two ends of

a link segment and automatically selecting the highest per

formance mode of operation supported by both devices.

Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83849ID supports four differ

ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high

est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83849ID can be controlled either by

internal register access or by the use of the AN_EN, AN1

and AN0 pins.

2.2.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 and AN1 determines whether the

DP83849ID is forced into a specific mode or Auto-Negotia

tion will advertise a specific ability (or set of abilities) as

given in

Table 1. These pins allow configuration options to

be selected without requiring internal register access.

The state of AN_EN, AN0 and AN1, upon power-up/reset,

determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or

reset can be changed at any time by writing to the Basic

Mode Control Register (BMCR) at address 00h.

2.2.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83849ID trans-

mits the abilities programmed into the Auto-Negotiation

Advertisement register (ANAR) at address 04h via FLP

Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-

Duplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution:

— (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex

— (3) 10BASE-T Full Duplex

— (4) 10BASE-T Half Duplex (Lowest Priority)

The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the

Auto-Negotiation process. When Auto-Negotiation is dis

abled, the Speed Selection bit in the BMCR controls

switching between 10 Mb/s or 100 Mb/s operation, and the

Duplex Mode bit controls switching between full duplex

operation and half duplex operation. The Speed Selection

and Duplex Mode bits have no effect on the mode of oper

ation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status

achieved.

The Basic Mode Status Register (BMSR) indicates the set

of available abilities for technology types, Auto-Negotiation

ability, and Extended Register Capability. These bits are

permanently set to indicate the full functionality of the

DP83849ID (only the 100BASE-T4 bit is not set since the

DP83849ID does not support that function).

The BMSR also provides status on:

— Whether or not Auto-Negotiation is complete

— Whether or not the Link Partner is advertising that a re-

mote fault has occurred

— Whether or not valid link has been established

— Support for Management Frame Preamble suppression

The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the

DP83849ID. All available abilities are transmitted by

default, but any ability can be suppressed by writing to the

Table 1. Auto-Negotiation Modes

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex

0 0 1 10BASE-T, Full-Duplex

0 1 0 100BASE-TX, Half-Duplex

0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mo0e

1 0 0 10BASE-T, Half/Full-Duplex

1 0 1 100BASE-TX, Half/Full-Duplex

1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

www.national.com 18

DP83849ID

ANAR. Updating the ANAR to suppress an ability is one

way for a management agent to change (restrict) the tech

nology that is used.

The Auto-Negotiation Link Partner Ability Register

(ANLPAR) at address 05h is used to receive the base link

code word as well as all next page code words during the

negotiation. Furthermore, the ANLPAR will be updated to

either 0081h or 0021h for parallel detection to either 100

Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indi-

cates additional Auto-Negotiation status. The ANER pro-

vides status on:

— Whether or not a Parallel Detect Fault has occurred

— Whether or not the Link Partner supports the Next Page

function

— Whether or not the DP83849ID supports the Next Page

function

— Whether or not the current page being exchanged by

Auto-Negotiation has been received

— Whether or not the Link Partner supports Auto-Negotia-

tion

2.2.3 Auto-Negotiation Parallel Detection

The DP83849ID supports the Parallel Detection function as

defined in the IEEE 802.3u specification. Parallel Detection

requires both the 10 Mb/s and 100 Mb/s receivers to moni

tor the receive signal and report link status to the Auto-

Negotiation function. Auto-Negotiation uses this informa

tion to configure the correct technology in the event that the

Link Partner does not support Auto-Negotiation but is

transmitting link signals that the 100BASE-TX or 10BASE-

T PMAs recognize as valid link signals.

If the DP83849ID completes Auto-Negotiation as a result of

Parallel Detection, bits 5 and 7 within the ANLPAR register

will be set to reflect the mode of operation present in the

Link Partner. Note that bits 4:0 of the ANLPAR will also be

set to 00001 based on a successful parallel detection to

indicate a valid 802.3 selector field. Software may deter

mine that negotiation completed via Parallel Detection by

reading a zero in the Link Partner Auto-Negotiation Able bit

once the Auto-Negotiation Complete bit is set. If configured

for parallel detect mode and any condition other than a sin

gle good link occurs then the parallel detect fault bit will be

set.

2.2.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted

at any time by setting bit 9 (Restart Auto-Negotiation) of the

BMCR to one. If the mode configured by a successful Auto-

Negotiation loses a valid link, then the Auto-Negotiation

process will resume and attempt to determine the configu

ration for the link. This function ensures that a valid config-

uration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a manage-

ment agent, will cause the DP83849ID to halt any transmit

data and link pulse activity until the break_link_timer

expires (~1500 ms). Consequently, the Link Partner will go

into link fail and normal Auto-Negotiation resumes. The

DP83849ID will resume Auto-Negotiation after the

break_link_timer has expired by issuing FLP (Fast Link

Pulse) bursts.

2.2.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83849ID has been ini-

tialized upon power-up as a non-auto-negotiating device

(forced technology), and it is then required that Auto-Nego-

tiation or re-Auto-Negotiation be initiated via software,

bit

12 (Auto-Negotiation Enable) of the Basic Mode Control

Auto-Negotiation function to take effect.

2.2.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately

2-3 seconds to complete. In addition, Auto-Negotiation with

next page should take approximately 2-3 seconds to com

plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full

description of the individual timers related to Auto-Negotia-

tion.

2.3 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to

determine the proper configuration for transmission and

reception of data and subsequently selects the appropriate

MDI pair for MDI/MDIX operation. The function uses a ran

dom seed to control switching of the crossover circuitry.

This implementation complies with the corresponding IEEE

802.3 Auto-Negotiation and Crossover Specifications.

Auto-MDIX is enabled by default and can be configured via

strap or via PHYCR (19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced

crossover can be achieved through the FORCE_MDIX bit,

bit 14 of PHYCR (19h) register.

Note: Auto-MDIX will not work in a forced mode of opera-

tion.

2.4 PHY Address

The 4 PHY address inputs pins are shown below.

The DP83849ID provides four address strap pins for deter-

mining the PHY addresses for ports A and B of the device.

The 4 address strap pins provide the upper four bits of the

PHY address. The lowest bit of the PHY address is depen

dent on the port. Port A has a value of 0 for the PHY

address bit 0 while port B has a value of 1. The PHY

address strap input pins are shown in

Tab le 2 .

The PHY address strap information is latched into the

PHYCR register (address 19h, bits [4:0]) at device power-

up and hardware reset. The PHY Address pins are shared

with the RXD pins. Each DP83849ID or port sharing an

Table 2. PHY Address Mapping

Pin # PHYAD Function RXD Function

4 PHYAD1 RXD0_A

5 PHYAD2 RXD1_A

58 PHYAD3 RXD0_B

57 PHYAD4 RXD1_B

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