"PCI-SIG发布U.2-SFF-8639-V4.0规范 4.0版本详解"

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The U.2-SFF-8639-V4.0 specification, also known as the PCI Express SFF-8639 Module Specification Revision 4.0, Version 0.5, was released on March 21, 2019, with an updated version on April 3, 2019. This specification is governed by the PCI-SIG® and provides guidelines for the design and implementation of U.2-SFF-8639-V4.0 compliant devices. The specification outlines the physical and electrical requirements for U.2-SFF-8639-V4.0 connectors and modules, ensuring interoperability and compatibility between different manufacturers' products. It covers aspects such as form factor, pin assignments, mechanical dimensions, and signal characteristics to enable the seamless integration of U.2-SFF-8639-V4.0 devices into various computing systems. It is important to note that PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein. They also assume no responsibility for any errors that may appear in this document and do not make a commitment to update the information contained therein. Users are advised to contact the PCI-SIG office to obtain the latest revision of this specification and address any questions regarding the PCI Express SFF-8639 Module. Overall, the U.2-SFF-8639-V4.0 specification plays a crucial role in standardizing the design and implementation of U.2-SFF-8639-V4.0 compliant devices, ensuring their compatibility and interoperability in the market. Its guidelines and requirements provide a framework for manufacturers to adhere to, ultimately benefiting end-users with reliable and seamless integration of U.2-SFF-8639-V4.0 devices into their computing systems.

SFF-8639 Connector Interface

PCI Express SFF-8639 Module

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Revision 4.0, Version 0.5

March 21April 3, 2019

1.7. Electrical Overview 295

The electrical specification covers Auxiliary signals, hot insertion and removal, power delivery, and 296

interconnect electrical budgets. The PCI Express Transmitter and Receiver electrical requirements 297

are specified in the PCI Express Base Specification. 298

In addition to those signals required to transmit/receive data on the PCI Express interface, there are 299

other signals that are available to implement the PCI Express interface in a system environment, or 300

to provide certain desired functions. These signals are referred to as the Auxiliary signals. They 301

include: 302

 Reference clock (REFCLK+/REFCLK-): this signal must be supplied by the system (see 303

Section 2.1.1). 304

 PRSNT#, IfDet#: SFF-8639 module presence -detect pins (required). 305

 PERST#: PCI Express reset, required. 306

 ACTIVITY#: Indicates activity of the SFF-8639 module, required. 307

 SMBus (SMBCLK and SMBDAT), System Management Bus (SMBus) Specification, optional. 308

 Wake (WAKE#): This signal is required only if the module/system supports wakeup and/or 309

the Optimized Buffer Flush/Fill (OBFF) mechanism. 310

 +3.3 Vaux: Auxiliary power, supports SMBus and wakeup functionality, optional. 311

 DualPortEn#: This signal is asserted to enable Dual port mode of the SFF-8639 module and 312

de-assert to default to a single x4 port, optional. 313

 REFCLKB+ and REFCLKB-: These reference clock signals - must be provided by the system 314

to the module if Dual port mode is enabled and the B-side port system is enabled. 315

 PERSTB#: This signal is required if Dual port mode is enabled by the system and supported by 316

the module. 317

 CLKREQ#: This signal is required if the module needs to control the clock or if L1 PM 318

Substates are supported; not supported if Dual port mode enabled. 319

 PWRDIS: This signal is asserted to disable power to the SFF-8639 module circuitry. 320

The signals REFCLK+, REFCLK-, REFCLKB+, REFCLKB-, SMBCLK, SMBDAT, PERST#, 321

PERSTB#, ACTIVITY#, DualPortEn#, CLKREQ#, PWRDIS, and WAKE# are described in 322

Chapter 2, Auxiliary Signals. The signals PRSNT# and IfDet# are described in Chapter 3, Hot 323

Insertion and Removal. The signal +3.3 Vaux is described in Chapter 4, Electrical Requirements. 324

Chapter 3, Hot Insertion and Removal; discusses the detailed implementation of PCI Express Hot-Plug. 325

Chapter 4, Electrical Requirements, specifies the SFF-8639 module electrical requirements, which 326

include power delivery and interconnect electrical budgets. Power is delivered from the system to 327

the module via the SFF-8639 connector, using two voltage rails: 328

+3.3 Vaux and +12 V. A +5 V power rail may be present on the SFF-8639 receptacle, but all details 329

are outside the scope of this specification. . Note that the +3.3 Vaux voltage rail is not required for 330

all platforms (see Section 4.1 for more information on the required usage of +3.3 Vaux). Chapter 4, 331

Electrical Requirements

also describes interconnect electrical budgets; focusing on the system and SFF-332

8639 module loss and jitter requirements. 333

PCI Express SFF-8639 Module | 19

356

2. Auxiliary Signals 357

The Auxiliary signals are provided on the SFF-8639 module connector interface to assist with 358

certain system-level functionality or implementation. The SFF-8639 module connector interface 359

supports the following Auxiliary signals: 360

 REFCLK+/REFCLK-: These are low voltage differential signals. A system board that supports 361

5.0 GT/s maximum rate signaling or 8.0 GT/s maximum rate signaling must provide a reference 362

clock that meets all requirements for the common clock architecture defined for the reference 363

clock in the PCI Express Base Specification and all the requirements defined in this specification. A 364

system board that only supports 2.5 GT/s signaling must meet all reference clock requirements in 365

this specification. The SFF-8639 system must comply with the system board reference clock 366

requirements specified in the PCI Express Base Specification and this specification. 367

368

Note: Reference Clock requirements for 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s signaling rates are

defined in this specification. Additional Reference Clock requirements for 5.0 GT/s and 8.0

GT/s signaling rates are defined in the PCI Express Base Specification.

369

 PERST#: This signal indicates when the applied main power is within the specified tolerance 370

and stable. PERST# goes inactive after a delay of T

PVPERL

time from the power rails achieving 371

specified tolerance on power up. PERST# is also asserted to reset the SFF-8639 module. 372

 WAKE#: This signal is an open-drain, active low signal that is driven low by a PCI Express 373

Function to re-activate the PCI Express Link Hierarchy's main power rails and reference clocks. 374

It is required on any SFF-8639 module or system board that supports wakeup functionality 375

compliant with this specification. WAKE# is also used by the system to signal to the PCI 376

Express Function in conjunction with the OBFF mechanism. 377

 SMBCLK (optional): This is the SMBus interface clock signal. It is an open-drain signal. 378

 SMBDAT (optional): This is the SMBus interface address/data signal. It is an open-drain signal. 379

 PRSNT#: This signal is the SFF-8639 module presence detect pin. See Chapter 3 for a detailed 380

description. 381

 IfDet#: This signal is the SFF-8639 module interface detect pin. See Chapter 3 for a detailed 382

description. 383

 ACTIVITY#: This signal indicates activity of the SFF-8639 module. 384

Auxiliary Signals

PCI Express SFF-8639 Module

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Revision 4.0, Version 0.5

March 21April 3, 2019

 DualPortEn# (optional): This signal is an open drain pulled high by the SFF-8639 module and 385

asserted low by the system to enable Dual port mode of the SFF-8639 module. 386

 REFCLKB+/REFCLKB- (optional): These are low voltage differential signals. Reference clock 387

for the B-side port interface of the SFF-8639 module. Required from the system if Dual port 388

mode is supported and DualPortEn# is asserted. All other REFCLK+/REFCLK- requirements 389

within this document must apply to REFCLKB+/REFCLKB- unless otherwise noted. Timing 390

requirements for REFCLK+/REFCLK- must apply to REFCLKB+/REFCLKB- with respect 391

to the applicable B-side port signals. 392

 PERSTB# (optional): This signal is reset for the B-side port interface of the SFF-8639 module. 393

Required from the system if Dual port mode is supported and DualPortEn# is asserted. All 394

other PERST# requirements within this document must apply to PERSTB# unless otherwise 395

noted. Timing requirements for PERST# must apply to PERSTB# with respect to the 396

applicable B-side port signals. 397

 CLKREQ# (optional): This is an open drain signal that enable the PCI Express Clock for the 398

SFF-8639 module and control entry into the L1 PM Substates. CLKREQ# is only valid when 399

the module is not in Dual port mode. 400

 PWRDIS (optional): This signal is used to disable power to the SFF-8639 module circuitry. 401

Note that the SMBus interface pins are optional for both the SFF-8639 module and the SFF-8639 402

system. If the optional management features are implemented, SMBCLK and SMBDAT are both 403

required. 404

2.1. Reference Clock 405

2.1.1. Low Voltage Swing, Differential Clocks 406

Differential clocks are used to reduce jitter and allow for future silicon fabrication process changes 407

and low voltage swing, as shown in Figure 2-1. The nominal single-ended swing for each clock is 408

0 V to 0.7 V and a nominal frequency of 100 MHz with a tolerance of ±300 ppm. The clock has a 409

defined crossover voltage range and monotonic edges through the input threshold regions as 410

specified in Chapter 4. 411

412

Note: If Dual port mode enabled, reference clock requirements apply to the applicable B-side port

signals (REFCLKB+ / REFCLKB-). All reference clock requirements apply independently to both

ports.

413

414

period

REFCLK–

REFCLK+

OM14741

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