14 The SPARC Architecture Manual: Version 8
Multithreaded programs where all threads are restricted to run on a single proces-
sor will behave the same on PSO and TSO as they would on a Strongly Con-
sistent machine.
Input/Output SPARC assumes that input/output registers are accessed via load/store alternate
instructions, normal load/store instructions, coprocessor instructions, or
read/write ancillary state register instructions (RDASR, WRASR). In the
load/store alternate instructions case, the I/O registers can only be accessed by
the supervisor. If normal load/store instructions, coprocessor instructions, or
read/write Ancillary State Register instructions are used, whether the I/O regis-
ters can be accessed outside of supervisor code or not is implementation-
dependent.
The contents and addresses of I/O registers are implementation-dependent.
Definitions of “real memory” and “I/O locations” are provided in Chapter 6,
“Memory Model”.
2.4. Traps
A trap is a vectored transfer of control to the operating system through a special
trap table that contains the first 4 instructions of each trap handler. The base
address of the table is established by software in an IU state register (the trap
base register, TBR). The displacement within the table is encoded in the type
number of each trap. Half of the table is reserved for hardware traps, and the
other half for software traps generated by trap (Ticc) instructions.
A trap causes the current window pointer (CWP) to advance to the next register
window and the hardware to write the program counters into two registers of the
new window. The trap handler can access the saved PC and nPC and, in general,
can freely use the 6 other local registers in the new window.
A trap may be caused by an instruction-induced exception, or by an external
interrupt request not directly related to a particular instruction. Before execut-
ing each instruction, the IU checks for pending exceptions and interrupt requests.
If any are present, the IU selects the one with the highest priority and causes a
corresponding trap to occur.
Trap Categories An exception or interrupt request can cause either a precise trap, a deferred trap,
or an interrupting trap.
A precise trap is induced by a particular instruction and occurs before any
program-visible state is changed by the trap-inducing instruction.
A deferred trap is also induced by a particular instruction, but unlike a precise
trap, it may occur after program-visible state is changed by the execution of one
or more instructions that follow the trap-inducing instruction. A deferred trap
may occur one or more instructions after the trap-inducing instruction is exe-
cuted. An implementation must provide sufficient supervisor-readable state
(called a deferred-trap queue) to enable it to emulate an instruction that caused
a deferred trap and to correctly resume execution of the process containing that
instruction.
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