Section number Title Page
10.1.5.2 Interrupt destinations..............................................................................................................447
10.1.5.3 Internal interrupt sources.......................................................................................................448
10.2 PIC external signal descriptions....................................................................................................................................450
10.2.1 Signal overview..........................................................................................................................................451
10.2.2 Detailed signal descriptions.......................................................................................................................451
10.3 PIC memory map/register definition............................................................................................................................452
10.3.1 Block revision register 1 (PIC_BRR1)......................................................................................................462
10.3.2 Block revision register 2 (PIC_BRR2)......................................................................................................462
10.3.3 Interprocessor n dispatch register (PIC_IPIDRn)......................................................................................463
10.3.4 Current task priority register (PIC_CTPR)................................................................................................464
10.3.5 Who am I register (PIC_WHOAMI).........................................................................................................465
10.3.6 Interrupt acknowledge register (PIC_IACK).............................................................................................465
10.3.7 End of interrupt register (PIC_EOI)...........................................................................................................466
10.3.8 Feature reporting register (PIC_FRR)........................................................................................................467
10.3.9 Global configuration register (PIC_GCR).................................................................................................468
10.3.10 Vendor identification register (PIC_VIR)..................................................................................................469
10.3.11 Processor core initialization register (PIC_PIR)........................................................................................469
10.3.12 Interprocessor interrupt n vector/priority register (PIC_IPIVPRn)...........................................................470
10.3.13 Spurious vector register (PIC_SVR)..........................................................................................................471
10.3.14 Timer frequency reporting register group X (PIC_TFRRn)......................................................................471
10.3.15 Global timer n current count register group A (PIC_GTCCRAn).............................................................472
10.3.16 Global timer n base count register group A (PIC_GTBCRAn).................................................................473
10.3.17 Global timer n vector/priority register group A (PIC_GTVPRAn)...........................................................474
10.3.18 Global timer n destination register group A (PIC_GTDRAn)...................................................................475
10.3.19 Timer control register group n (PIC_TCRn)..............................................................................................475
10.3.20 External interrupt summary register (PIC_ERQSR)..................................................................................478
10.3.21 IRQ_OUT_B summary register 0 (PIC_IRQSR0)....................................................................................478
10.3.22 IRQ_OUT_B summary register 1 (PIC_IRQSR1)....................................................................................479
10.3.23 IRQ_OUT_B summary register 2 (PIC_IRQSR2)....................................................................................479
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
16 Freescale Semiconductor, Inc.