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首页Cyclone IV FPGA与P1022QorIQ处理器:低功耗与高性能解决方案
“P1022RM.pdf”是Freescale Semiconductor公司关于P1022 QorIQ Integrated Processor的参考手册,适用于P1022和P1013型号。该处理器集成了Power Architecture e500v2双核处理器,适用于媒体、通信和工业应用。
本手册详细介绍了P1022芯片的功能特性,包括关键性能参数、芯片级功能、应用示例和架构概述。其中,关键性能参数涉及了低功耗设计、高性能CPU核心、DDR2/DDR3内存控制器、三速以太网控制器(支持SGMII, RMII, RGMII)、安全数字接口、USB 2.0接口、音频/视频接口、PCI Express控制器以及对IEEE 1588精确时间协议的支持,用于网络同步。
在架构概述部分,手册详细阐述了e500v2核心和内存单元的设计,e500一致性模块(ECM)和地址映射,集成安全引擎(SEC),增强型三速以太网控制器(包含对IEEE 1588的集成),通用串行总线(USB 2.0)接口,增强型安全数字主机控制器,时分复用(TDM)接口,显示接口单元(DIU),同步串行接口(SSI),串行外围接口(SPI),以及DDR SDRAM控制器。这些组件共同构建了一个强大的通信处理器,能够在各种应用场景中提供高效能和低功耗的解决方案。
应用示例部分提到了多功能打印机应用、数字标牌应用和网络附加存储应用,展示P1022芯片如何在不同领域中满足不同的需求。例如,多功能打印机可能利用其高速数据处理能力;数字标牌应用可能利用其多媒体接口和网络连接;网络附加存储应用则可能依赖其高效的网络控制器和大容量内存接口。
P1022 QorIQ Integrated Processor是一款高度集成的处理器,适用于要求高带宽、低功耗和丰富接口的系统设计。它提供了丰富的通信协议和接口支持,能够满足现代工业和通信系统的复杂需求。对于P1013单核设备,虽然缺少一个CPU核心,但其他主要功能和特性与P1022相同。这份参考手册是理解并有效利用P1022和P1013芯片的关键资源。
Section number Title Page
10.1.5.2 Interrupt destinations..............................................................................................................447
10.1.5.3 Internal interrupt sources.......................................................................................................448
10.2 PIC external signal descriptions....................................................................................................................................450
10.2.1 Signal overview..........................................................................................................................................451
10.2.2 Detailed signal descriptions.......................................................................................................................451
10.3 PIC memory map/register definition............................................................................................................................452
10.3.1 Block revision register 1 (PIC_BRR1)......................................................................................................462
10.3.2 Block revision register 2 (PIC_BRR2)......................................................................................................462
10.3.3 Interprocessor n dispatch register (PIC_IPIDRn)......................................................................................463
10.3.4 Current task priority register (PIC_CTPR)................................................................................................464
10.3.5 Who am I register (PIC_WHOAMI).........................................................................................................465
10.3.6 Interrupt acknowledge register (PIC_IACK).............................................................................................465
10.3.7 End of interrupt register (PIC_EOI)...........................................................................................................466
10.3.8 Feature reporting register (PIC_FRR)........................................................................................................467
10.3.9 Global configuration register (PIC_GCR).................................................................................................468
10.3.10 Vendor identification register (PIC_VIR)..................................................................................................469
10.3.11 Processor core initialization register (PIC_PIR)........................................................................................469
10.3.12 Interprocessor interrupt n vector/priority register (PIC_IPIVPRn)...........................................................470
10.3.13 Spurious vector register (PIC_SVR)..........................................................................................................471
10.3.14 Timer frequency reporting register group X (PIC_TFRRn)......................................................................471
10.3.15 Global timer n current count register group A (PIC_GTCCRAn).............................................................472
10.3.16 Global timer n base count register group A (PIC_GTBCRAn).................................................................473
10.3.17 Global timer n vector/priority register group A (PIC_GTVPRAn)...........................................................474
10.3.18 Global timer n destination register group A (PIC_GTDRAn)...................................................................475
10.3.19 Timer control register group n (PIC_TCRn)..............................................................................................475
10.3.20 External interrupt summary register (PIC_ERQSR)..................................................................................478
10.3.21 IRQ_OUT_B summary register 0 (PIC_IRQSR0)....................................................................................478
10.3.22 IRQ_OUT_B summary register 1 (PIC_IRQSR1)....................................................................................479
10.3.23 IRQ_OUT_B summary register 2 (PIC_IRQSR2)....................................................................................479
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
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Section number Title Page
10.3.24 Critical interrupt summary register 0 (PIC_CISR0)..................................................................................480
10.3.25 Critical interrupt summary register 1 (PIC_CISR1)..................................................................................480
10.3.26 Critical interrupt summary register 2 (PIC_CISR2)..................................................................................481
10.3.27 Performance monitor n mask register 0 (PIC_PMnMR0).........................................................................481
10.3.28 Performance monitor n mask register 1 (PIC_PMnMR1).........................................................................482
10.3.29 Performance monitor n mask register 2 (PIC_PMnMR2).........................................................................482
10.3.30 Message register n (PIC_MSGRn)............................................................................................................483
10.3.31 Message enable register (PIC_MER).........................................................................................................483
10.3.32 Message status register (PIC_MSR)..........................................................................................................484
10.3.33 Shared message signaled interrupt register n (PIC_MSIRn).....................................................................485
10.3.34 Shared message signaled interrupt status register (PIC_MSISR)..............................................................485
10.3.35 Shared message signaled interrupt index register (PIC_MSIIR)...............................................................486
10.3.36 Global timer n current count register group B (PIC_GTCCRBn).............................................................487
10.3.37 Global timer n base count register group B (PIC_GTBCRBn).................................................................488
10.3.38 Global timer n vector/priority register group B (PIC_GTVPRBn)............................................................489
10.3.39 Global timer n destination register group B (PIC_GTDRBn)...................................................................490
10.3.40 Message register n (PIC_MSGRan)...........................................................................................................490
10.3.41 Message enable register (PIC_MERa).......................................................................................................491
10.3.42 Message status register (PIC_MSRa)........................................................................................................492
10.3.43 External interrupt n (IRQn) vector/priority register (PIC_EIVPRn).........................................................492
10.3.44 External interrupt n (IRQn) destination register (PIC_EIDRn).................................................................494
10.3.45 Internal interrupt n vector/priority register (PIC_IIVPRn)........................................................................495
10.3.46 Internal interrupt n destination register (PIC_IIDRn)................................................................................496
10.3.47 Messaging interrupt n (MSGn) vector/priority register (PIC_MIVPRn)...................................................497
10.3.48 Messaging interrupt n (MSGn) destination register (PIC_MIDRn)..........................................................498
10.3.49 Shared message signaled interrupt vector/priority register n (PIC_MSIVPRn)........................................499
10.3.50 Shared message signaled interrupt destination register n (PIC_MSIDRn)................................................500
10.3.51 Processor core 0 interprocessor n dispatch register (PIC_IPIDR_CPU0n)...............................................501
10.3.52 Processor core current task priority register 0 (PIC_CTPR_CPU0)..........................................................501
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
Freescale Semiconductor, Inc. 17
Section number Title Page
10.3.53 Processor core 0 who am I register (PIC_WHOAMI_CPU0)...................................................................502
10.3.54 Processor core 0 interrupt acknowledge register (PIC_IACK_CPU0)......................................................503
10.3.55 Processor core 0 end of interrupt register (PIC_EOI_CPU0)....................................................................504
10.3.56 Processor core 1 interprocessor n dispatch register (PIC_IPIDR_CPU1n)...............................................505
10.3.57 Processor core 1 current task priority register (PIC_CTPR_CPU1)..........................................................505
10.3.58 Processor core 1 who am I register (PIC_WHOAMI_CPU1)...................................................................506
10.3.59 Processor core 1 interrupt acknowledge register (PIC_IACK_CPU1)......................................................507
10.3.60 Processor core 1 end of interrupt register (PIC_EOI_CPU1)....................................................................508
10.4 Functional description...................................................................................................................................................508
10.4.1 Programming model considerations...........................................................................................................508
10.4.1.1 Global registers......................................................................................................................508
10.4.1.2 Global timer registers.............................................................................................................509
10.4.1.3 IRQ_OUT_B and critical interrupt summary registers..........................................................509
10.4.1.4 Performance monitor mask registers (PMMRs)....................................................................510
10.4.1.5 Message registers...................................................................................................................510
10.4.1.6 Shared message signaled registers.........................................................................................510
10.4.1.7 Interrupt source configuration registers.................................................................................510
10.4.1.8 Per-CPU (private access) registers.........................................................................................512
10.4.2 Flow of interrupt control............................................................................................................................513
10.4.2.1 Interrupts routed to cint or IRQ_OUT_B...............................................................................514
10.4.2.2 Interrupts routed to int............................................................................................................514
10.4.2.2.1 Interrupt source priority..................................................................................517
10.4.2.2.2 Interrupt acknowledge....................................................................................517
10.4.2.2.3 Spurious vector generation.............................................................................518
10.4.2.2.4 Nesting of interrupts.......................................................................................518
10.4.3 Interprocessor interrupts............................................................................................................................519
10.4.4 Message interrupts.....................................................................................................................................519
10.4.5 Shared message signaled interrupts...........................................................................................................519
10.4.6 PCI Express INTx/IRQn sharing...............................................................................................................520
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
18 Freescale Semiconductor, Inc.
Section number Title Page
10.4.7 Global timers..............................................................................................................................................521
10.4.8 Resets.........................................................................................................................................................521
10.4.9 Resetting the PIC.......................................................................................................................................521
10.4.9.1 Processor core initialization...................................................................................................522
10.5 Initialization/application information...........................................................................................................................522
10.5.1 Programming guidelines............................................................................................................................522
10.5.1.1 PIC registers...........................................................................................................................522
10.5.1.2 Changing interrupt source configuration...............................................................................524
Chapter 11
I2C Interfaces
11.1 Overview.......................................................................................................................................................................525
11.2 Introduction to I2C........................................................................................................................................................525
11.2.1 What is the I2C module?............................................................................................................................525
11.2.2 I2C module block diagram.........................................................................................................................526
11.2.3 Features .....................................................................................................................................................526
11.2.4 Advantages of the I2C bus.........................................................................................................................527
11.2.5 Modes of operation....................................................................................................................................527
11.2.6 I2C-specific conditions..............................................................................................................................527
11.3 I2C external signal descriptions....................................................................................................................................528
11.3.1 Signal overview..........................................................................................................................................528
11.3.2 Detailed signal descriptions.......................................................................................................................528
11.4 I2C memory map/register definition.............................................................................................................................529
11.4.1 I2C address register (I2Cx_I2CADR)........................................................................................................530
11.4.2 I2C frequency divider register (I2Cx_I2CFDR)........................................................................................531
11.4.3 I2C control register (I2Cx_I2CCR)............................................................................................................533
11.4.4 I2C status register (I2Cx_I2CSR)..............................................................................................................534
11.4.5 I2C data register (I2Cx_I2CDR)................................................................................................................535
11.4.6 I2C digital filter sampling rate register (I2Cx_I2CDFSRR)......................................................................536
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
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Section number Title Page
11.5 Functional description...................................................................................................................................................536
11.5.1 Transaction protocol..................................................................................................................................536
11.5.1.1 START condition...................................................................................................................537
11.5.1.2 Slave address transmission.....................................................................................................537
11.5.1.3 Repeated START condition...................................................................................................538
11.5.1.4 STOP condition......................................................................................................................539
11.5.1.5 Protocol implementation details.............................................................................................539
11.5.1.5.1 Transaction monitoring-implementation details.............................................539
11.5.1.5.2 Control transfer-implementation details.........................................................539
11.5.1.6 Address compare-implementation details..............................................................................540
11.5.2 Arbitration procedure.................................................................................................................................541
11.5.2.1 Arbitration control..................................................................................................................541
11.5.3 Handshaking...............................................................................................................................................542
11.5.4 Clock control..............................................................................................................................................542
11.5.4.1 Clock synchronization............................................................................................................542
11.5.4.2 Input synchronization and digital filter..................................................................................543
11.5.4.2.1 Input signal synchronization...........................................................................543
11.5.4.2.2 Filtering of SCL and SDA lines......................................................................543
11.5.4.3 Clock stretching.....................................................................................................................543
11.5.5 Boot sequencer mode.................................................................................................................................544
11.5.5.1 EEPROM calling address.......................................................................................................545
11.5.5.2 EEPROM data format............................................................................................................545
11.6 Initialization/application information...........................................................................................................................548
11.6.1 Initialization sequence................................................................................................................................548
11.6.2 Generation of START................................................................................................................................549
11.6.3 Post-transfer software response.................................................................................................................549
11.6.4 Generation of STOP...................................................................................................................................550
11.6.5 Generation of repeated START.................................................................................................................550
11.6.6 Generation of SCL when SDA low............................................................................................................550
P1022 QorIQ Integrated Processor Reference Manual, Rev. 2, 04/2013
20 Freescale Semiconductor, Inc.
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