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首页飞思卡尔KL46单片机参考手册:底层开发必备
飞思卡尔KL46单片机参考手册:底层开发必备
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更新于2024-07-22
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"飞思卡尔KL46P121M48SF4RM是针对飞思卡尔KL46系列单片机的参考资料,主要适用于MKL46Z128VLH4、MKL46Z256VLH4、MKL46Z256VMP4等型号的底层开发。这份文档详细介绍了KL46子系列单片机的特性和功能,包含了从芯片配置到模块功能等多个方面的内容,旨在为开发者提供全面的技术支持。"
飞思卡尔KL46系列单片机是基于ARMCortex-M0+内核的微控制器,具有高效能和低功耗的特点。这份参考手册首先介绍了文档的目的和受众,明确了文档是为了解决KL46系列单片机在开发过程中的各种问题,适用于电子工程师、嵌入式系统开发者等专业人士。
文档中详细列出了KL46子系列的各项功能模块,包括:
1. **ARMCortex-M0+核心模块**:这是处理器的核心,提供基本的指令执行和处理能力。
2. **系统模块**:包括电源管理、中断控制器、时钟系统等,它们是系统运行的基础。
3. **内存和内存接口**:涵盖闪存、SRAM等存储资源及其访问机制。
4. **时钟系统**:负责为各个模块提供所需的时钟信号,可进行频率管理和节能控制。
5. **安全和完整性模块**:可能包含加密硬件、安全特性,确保数据的安全性和系统的可靠性。
6. **模拟模块**:如ADC、DAC等,用于处理模拟信号,将数字信息转化为模拟信号或将模拟信号转化为数字信息。
7. **定时器模块**:用于计时、事件触发等多种用途。
8. **通信接口**:如I2C、SPI、UART等,用于设备间的通信。
9. **人机交互接口**:如GPIO、LCD控制器等,用于实现与外部设备的交互。
此外,手册还提供了订购信息,列出了可订购的不同封装和配置的芯片型号,方便用户根据项目需求选择合适的部件。
在芯片配置部分,文档会详细阐述如何设置和配置KL46单片机的各项功能,包括初始化、外设配置等,帮助开发者理解并充分利用芯片的各种特性,从而进行高效的底层程序设计和系统搭建。
总结来说,"KL46P121M48SF4RM"是一份全面介绍飞思卡尔KL46系列单片机的参考资料,对于需要进行该系列单片机开发的工程师来说,是不可或缺的工具书,能够提供深入的硬件理解和技术支持。
Section number Title Page
24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................390
24.3.7 MCG Status Register (MCG_S)..................................................................................................................391
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................393
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................394
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................394
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................395
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................395
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................396
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................396
24.4 Functional description...................................................................................................................................................397
24.4.1 MCG mode state diagram............................................................................................................................397
24.4.2 Low Power Bit Usage..................................................................................................................................402
24.4.3 MCG Internal Reference Clocks..................................................................................................................402
24.4.4 External Reference Clock............................................................................................................................403
24.4.5 MCG Fixed frequency clock .......................................................................................................................403
24.4.6 MCG PLL clock ..........................................................................................................................................403
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................404
24.5 Initialization / Application information........................................................................................................................405
24.5.1 MCG module initialization sequence...........................................................................................................405
24.5.2 Using a 32.768 kHz reference......................................................................................................................407
24.5.3 MCG mode switching..................................................................................................................................408
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................417
25.2 Features and Modes......................................................................................................................................................417
25.3 Block Diagram..............................................................................................................................................................418
25.4 OSC Signal Descriptions..............................................................................................................................................418
25.5 External Crystal / Resonator Connections....................................................................................................................419
25.6 External Clock Connections.........................................................................................................................................420
KL46 Sub-Family Reference Manual, Rev. 3, July 2013
16 Freescale Semiconductor, Inc.
Section number Title Page
25.7 Memory Map/Register Definitions...............................................................................................................................421
25.7.1 OSC Memory Map/Register Definition.......................................................................................................421
25.8 Functional Description..................................................................................................................................................422
25.8.1 OSC Module States......................................................................................................................................422
25.8.2 OSC Module Modes.....................................................................................................................................424
25.8.3 Counter.........................................................................................................................................................426
25.8.4 Reference Clock Pin Requirements.............................................................................................................426
25.9 Reset..............................................................................................................................................................................426
25.10 Low Power Modes Operation.......................................................................................................................................427
25.11 Interrupts.......................................................................................................................................................................427
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................429
26.1.1 Overview......................................................................................................................................................429
26.1.2 Features........................................................................................................................................................429
26.2 Modes of operation.......................................................................................................................................................430
26.3 External signal description............................................................................................................................................430
26.4 Memory map and register descriptions.........................................................................................................................430
26.5 Functional description...................................................................................................................................................430
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................433
27.1.1 Features........................................................................................................................................................434
27.1.2 Block Diagram.............................................................................................................................................434
27.1.3 Glossary.......................................................................................................................................................435
27.2 External Signal Description..........................................................................................................................................436
27.3 Memory Map and Registers..........................................................................................................................................436
27.3.1 Flash Configuration Field Description.........................................................................................................436
KL46 Sub-Family Reference Manual, Rev. 3, July 2013
Freescale Semiconductor, Inc. 17
Section number Title Page
27.3.2 Program Flash IFR Map...............................................................................................................................437
27.3.3 Register Descriptions...................................................................................................................................438
27.4 Functional Description..................................................................................................................................................446
27.4.1 Flash Protection............................................................................................................................................447
27.4.2 Interrupts......................................................................................................................................................447
27.4.3 Flash Operation in Low-Power Modes........................................................................................................448
27.4.4 Functional Modes of Operation...................................................................................................................448
27.4.5 Flash Reads and Ignored Writes..................................................................................................................448
27.4.6 Read While Write (RWW)...........................................................................................................................449
27.4.7 Flash Program and Erase..............................................................................................................................449
27.4.8 Flash Command Operations.........................................................................................................................449
27.4.9 Margin Read Commands.............................................................................................................................454
27.4.10 Flash Command Description........................................................................................................................455
27.4.11 Security........................................................................................................................................................468
27.4.12 Reset Sequence............................................................................................................................................470
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................471
28.1.1 Features........................................................................................................................................................471
28.1.2 Block diagram..............................................................................................................................................472
28.2 ADC signal descriptions...............................................................................................................................................473
28.2.1 Analog Power (VDDA)...............................................................................................................................474
28.2.2 Analog Ground (VSSA)...............................................................................................................................474
28.2.3 Voltage Reference Select.............................................................................................................................474
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................475
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................475
28.3 Memory map and register definitions...........................................................................................................................475
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................476
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................479
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Section number Title Page
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................481
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................482
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................483
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................484
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................486
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................488
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................488
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................489
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................489
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................490
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................490
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................491
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................491
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................492
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................492
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................493
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................493
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................494
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................494
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................495
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................495
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................496
28.4 Functional description...................................................................................................................................................496
28.4.1 Clock select and divide control....................................................................................................................497
28.4.2 Voltage reference selection..........................................................................................................................497
28.4.3 Hardware trigger and channel selects..........................................................................................................498
28.4.4 Conversion control.......................................................................................................................................499
28.4.5 Automatic compare function........................................................................................................................507
28.4.6 Calibration function.....................................................................................................................................508
KL46 Sub-Family Reference Manual, Rev. 3, July 2013
Freescale Semiconductor, Inc. 19
Section number Title Page
28.4.7 User-defined offset function........................................................................................................................509
28.4.8 Temperature sensor......................................................................................................................................511
28.4.9 MCU wait mode operation...........................................................................................................................511
28.4.10 MCU Normal Stop mode operation.............................................................................................................512
28.4.11 MCU Low-Power Stop mode operation......................................................................................................513
28.5 Initialization information..............................................................................................................................................513
28.5.1 ADC module initialization example............................................................................................................513
28.6 Application information................................................................................................................................................515
28.6.1 External pins and routing.............................................................................................................................515
28.6.2 Sources of error............................................................................................................................................517
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................523
29.2 CMP features................................................................................................................................................................523
29.3 6-bit DAC key features.................................................................................................................................................524
29.4 ANMUX key features...................................................................................................................................................525
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................525
29.6 CMP block diagram......................................................................................................................................................526
29.7 Memory map/register definitions..................................................................................................................................528
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................528
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................529
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................531
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................531
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................532
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................533
29.8 Functional description...................................................................................................................................................534
29.8.1 CMP functional modes.................................................................................................................................534
29.8.2 Power modes................................................................................................................................................543
29.8.3 Startup and operation...................................................................................................................................544
KL46 Sub-Family Reference Manual, Rev. 3, July 2013
20 Freescale Semiconductor, Inc.
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