ES9038PRO旗舰8声道32位HyperStream II DAC：业界最高性能音频解码器
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更新于2024-07-05
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ES9038PRO是一款由ESS Technology公司推出的旗舰级8通道HyperStream II 32位音频解码器，专为Hi-Fi发烧友和专业音频应用设计，如SACD播放器、蓝光播放器、数字前置放大器、A/V接收机、录音棚控制台和数字音频工作站等。这款产品以其卓越的性能和创新技术脱颖而出。
ES9038PRO的核心特点包括：
1. **专利的32位HyperStream II DAC**：它具有业界领先的性能，能够实现高达140分贝的信噪比（SNR）在单声道模式下，以及令人惊叹的-122分贝的总谐波失真加噪声（THD+N）。这种高分辨率处理确保了无与伦比的动态范围和极低的失真度，满足最苛刻的音频品质追求。
2. **时间域去抖动技术**：专利的时域去抖动器能有效消除输入时钟抖动，提供无与伦比的音质清晰度，确保了音频信号的纯净度。
3. **64位累加器与32位处理**：通过采用先进的数字信号处理技术，信号经过零失真处理，确保了音频的准确性。
4. **多样化的数字输入接口**：支持包括SPDIF、I2S、LJ、RJ16-32位等多种格式，最高可处理768kHz的PCM和DSD256，甚至支持高达1.536MHz的外部过采样滤波，兼容Master和Slave时钟模式，灵活性极高。
5. **集成的数字信号处理器功能**：包括无点击软切换、平滑的静音处理和输出音量调整，还有可编程的零检测功能，以及对32kHz、44.1kHz和48kHz采样率的补偿，提升了整体音频体验。
6. **可定制的输出配置**：用户可以根据需求选择单声道、立体声或8声道输出，满足不同应用场景下的输出需求。
ES9038PRO的这些特性使其成为高端音频设备的理想选择，无论是追求极致音质的发烧友还是寻求高效音频解决方案的专业工程师，都能在这款解码器中找到满意的技术支撑。它的出现重新定义了模拟音频的边界，推动了音频行业的技术革新。
CONFIDENTIAL ADVANCE INFORMATION v3.7
February 8, 2021
ES9038PRO Flagship 32-Bit HyperStream® II 8-Channel Audio DAC
ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM
wwwWWW.ESSTECH.COM
10
Time Domain Jitter Eliminator and DPLL
By default, the DAC works in Jitter Eliminator mode allowing the audio interface timing to be asynchronous to MCLK. A DPLL
constantly updates the FSR/MCLK ratio to calculate the true 32-bit timing of the incoming audio samples allowing the ESS
patented Time Domain Jitter Eliminator to remove any distortion caused by jitter.
• The DPLL acquisition speed can be set by lock_speed in Register 10: Master Mode and Sync Configuration.
• The PCM/SPDIF DPLL bandwidth can be set via dpll_bw_serial in Register 12: Jitter Eliminator / DPLL Bandwidth
• The DSD DPLL bandwidth can be set via dpll_bw_dsd in Register 12: Jitter Eliminator / DPLL Bandwidth
For best performance, the DPLL bandwidth should be set to the minimum setting that will keep the DPLL reliably in lock.
Sample Rate Calculation
The raw sample rate (FSR) can be calculated from Register 66-69 : DPLL Number using the following formula:
Synchronous Mode (PCM mode only)
The DPLL can be bypassed if the incoming PCM audio is synchronous to MCLK with the relationship MCLK=128FSR. This
can be enabled via 128fs_mode in Register 10: Master Mode and Sync Configuration.
DAC Full-Scale Gain Calibration
DAC gain calibration enables uniform output level across multiple chips by compensating for chip-to-chip gain variations.
The DAC full-scale gain-calibration system works by comparing an internal resistor to an external precision resistor of known
value. The two resistors are set up as a voltage divider that is connected between power and ground. The value of the
internal resistor changes with semiconductor process variations so by measuring the divider’s voltage output, using an ADC,
the process variation from nominal can be measured and this is used to correct the DAC gain. As all the DAC channels are
on the same monolithic chip, the channel-to-channel gain variation is very small and does not need to be trimmed.
There are two ADCs and either of the ADC inputs can be used to drive the auto-calibration circuit. The circuit uses the ADC
value, as decimated by the internal programmable decimation filters, to scale the master_trim value. Master_trim can be
programmed as normal but will be scaled by the ADC value when in automatic-calibration mode. In this mode, master_trim
can be set once by enabling automatic calibration, and the DAC output levels will be consistent across all DAC devices.
• Full-scale gain-calibration is enabled using calib_en in Register 63: Auto Calibration.
• calib_sel in Register 63: Auto Calibration selects which ADC to use
• calib_latch in Register 63: Auto Calibration determines whether to use the new ADC correction value or ignore it.
• ADC values update at the ADC_CLK rate which is also programmable in Register 46: ADC Configuration.
The ADC decimation filters may also be programmed to a lower bandwidth to help smooth out any voltage transients on the
divider output.
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