深入理解ARM A-profile架构：参考手册解析

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"ARM A 、R Profile架构参考手册（v8、v9）" ARM A Profile架构参考手册是针对ARM Cortex-A系列处理器的权威技术文档，它深入介绍了ARM架构的高级特性，是中高级开发者和系统架构人员的重要学习资料。手册涵盖了从v8到v9版本的架构更新，这些版本在现代高性能计算、移动设备和数据中心应用中广泛使用。手册的主要内容可能包括但不限于以下几个方面： 1. **ARMv8-A架构**：这是ARM首次引入64位指令集的架构，也称为AArch64。它提供了更高效的数据处理能力，支持更大的内存地址空间，并引入了新的安全和虚拟化特性。 2. **ARMv9架构**：作为v8的后续，v9架构进一步增强了性能、安全性和效率。它可能包括新的指令集扩展，如SVE2（ Scalable Vector Extension 2），用于高性能计算和AI应用；改进的内存模型，以提升多核同步；以及增强的安全功能，如TrustZone技术的扩展。 3. **处理器核心设计**：手册详细阐述了Cortex-A系列核心的设计原理，包括不同级别的缓存层次结构、预取机制、超标量执行、乱序执行单元等，这些都是提升处理器性能的关键元素。 4. **系统级特性**：除了核心设计，还可能涵盖内存管理单元（MMU）、中断控制器、电源管理单元等系统级组件的工作原理，这些对于理解和优化整个系统性能至关重要。 5. **编程模型**：A Profile架构的编程模型，包括寄存器布局、指令集说明、异常和中断处理机制，以及如何在AArch64模式下进行程序开发。 6. **安全与虚拟化**：ARMv8和v9架构强调了安全性，如TrustZone技术，允许创建安全的隔离环境。同时，虚拟化技术的增强使得在单一硬件平台上运行多个操作系统实例成为可能。 7. **性能优化指南**：手册通常会包含一些性能调优的指导原则，帮助开发者充分利用ARM处理器的潜力，包括编译器优化选项、并行化策略和内存访问最佳实践。 8. **开发者工具支持**：介绍如何使用调试工具、性能分析器和其他开发工具来理解和优化基于ARM A Profile架构的应用程序。由于手册的难度评级为5星，阅读者需要有一定的基础，包括计算机体系结构、操作系统原理和编程经验。尽管挑战性较大，但其高价值性使得深入理解ARM A Profile架构对于设计高效、安全的嵌入式系统或服务器平台具有重要意义。

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Appendix K15 Legacy Feature Naming Convention

K15.1 The Armv8.0 architecture ............................................................................ K15-11798

K15.2 The Armv8.1 architecture extension ............................................................ K15-11799

K15.3 The Armv8.2 architecture extension ............................................................ K15-11800

K15.4 The Armv8.3 architecture extension ............................................................ K15-11802

K15.5 The Armv8.4 architecture extension ............................................................ K15-11803

K15.6 The Armv8.5 architecture extension ............................................................ K15-11804

K15.7 The Armv8.6 architecture extension ............................................................ K15-11805

Appendix K16 Arm Pseudocode Definition

K16.1 About the Arm pseudocode ......................................................................... K16-11808

K16.2 Pseudocode for instruction descriptions ...................................................... K16-11809

K16.3 Data types ................................................................................................... K16-11811

K16.4 Operators .................................................................................................... K16-11816

K16.5 Statements and control structures .............................................................. K16-11822

K16.6 Built-in functions .......................................................................................... K16-11827

K16.7 Miscellaneous helper procedures and functions ......................................... K16-11830

K16.8 Arm pseudocode definition index ................................................................ K16-11832

Appendix K17 Registers Index

K17.1 Introduction and register disambiguation .................................................... K17-11836

K17.2 Alphabetical index of AArch64 registers and System instructions .............. K17-11848

K17.3 Functional index of AArch64 registers and System instructions ................. K17-11868

K17.4 Alphabetical index of AArch32 registers and System instructions .............. K17-11889

K17.5 Functional index of AArch32 registers and System instructions ................. K17-11899

K17.6 Alphabetical index of memory-mapped registers ........................................ K17-11911

K17.7 Functional index of memory-mapped registers ........................................... K17-11923

Glossary

Preface

About this Manual

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About this Manual

This Manual describes the Arm

architecture v8, Armv8, and the Arm

architecture v9, Armv9. The architecture

describes the operation of an Armv8-A and an Armv9-A Processing element (PE), and this Manual includes

descriptions of:

• The two Execution states, AArch64 and AArch32.

• The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, which are compatible with earlier versions of the

Arm architecture.

— In AArch64 state, the A64 instruction set.

• The states that determine how a PE operates, including the current Exception level and Security state, and in

AArch32 state the PE mode.

• The Exception model.

• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.

• The memory model, that defines memory ordering and memory management. This Manual covers the Arm

A architecture profile, both Armv8-A and Armv9-A, that defines a Virtual Memory System Architecture

(VMSA).

• The programmers’ model, and its interfaces to System registers that control most PE and memory system

features, and provide status information.

• The Advanced SIMD and floating-point instructions, which provide high-performance:

— Single-precision, half-precision, and double-precision floating-point operations.

— Conversions between double-precision, single-precision, and half-precision floating-point values.

— Integer, single-precision floating-point, and half-precision floating-point vector operations in all

instruction sets.

— Double-precision floating-point vector operations in the A64 instruction set.

• The security model, which provides two Security states to support Secure applications.

• The virtualization model.

• The Debug architecture, which provides software access to debug features.

This Manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in

textual form. However, this Manual is not a tutorial for Arm assembler language, nor does it describe Arm assembler

language, except at a very basic level. To make effective use of Arm assembler language, read the documentation

supplied with the assembler being used.

This Manual is organized into parts:

Part A Provides an introduction to the Arm architecture, and an overview of the AArch64 and AArch32

Execution states.

Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.

It describes the application level view of the programmers’ model and the memory model.

Part C Describes the A64 instruction set, which is available in the AArch64 Execution state. The

descriptions for each instruction also include the precise effects of each instruction when executed

at EL0, described as unprivileged execution, including any restrictions on its use, and how the

effects of the instruction differ at higher Exception levels. This information is of primary importance

to authors and users of compilers, assemblers, and other programs that generate Arm machine code.

Part D Describes the system level view of the AArch64 Execution state. It includes details of the System

registers, most of which are not accessible from EL0, and the system level view of the programmers’

model and the memory model. This part includes the description of self-hosted debug.

Preface

About this Manual

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Part E Describes the application level view of the AArch32 Execution state, meaning the view from the

EL0. It describes the application level view of the programmers’ model and the memory model.

Note

In AArch32 state, execution at EL0 is execution in User mode.

Part F Describes the T32 and A32 instruction sets, which are available in the AArch32 Execution state.

These instruction sets are backwards-compatible with earlier versions of the Arm architecture. This

part describes the precise effects of each instruction when executed in User mode, described as

unprivileged execution or execution at EL0, including any restrictions on its use, and how the effects

of the instruction differ at higher Exception levels. This information is of primary importance to

authors and users of compilers, assemblers, and other programs that generate Arm machine code.

Note

User mode is the only mode where software execution is unprivileged.

Part G Describes the system level view of the AArch32 Execution state, which is generally compatible with

earlier versions of the Arm architecture. This part includes details of the System registers, most of

which are not accessible from EL0, and the instruction interface to those registers. It also describes

the system level view of the programmers’ model and the memory model.

Part H Describes the Debug architecture for external debug. This provides configuration, breakpoint and

watchpoint support, and a Debug Communications Channel (DCC) to a debug host.

Part I Describes additional features of the architecture that are not closely coupled to a processing element

(PE), and therefore are accessed through memory-mapped interfaces. Some of these features are

OPTIONAL.

Part J Provides pseudocode that describes various features of the Arm architecture.

Part K, Appendixes

Provide additional information. Some appendixes give information that is not part of the A-profile

architectural requirements. The cover page of each appendix indicates its status.

Glossary Defines terms used in this Manual that have a specialized meaning.

Note

Terms that are generally well understood in the microelectronics industry are not included in the

Glossary.

Preface

Using this Manual

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Using this Manual

The information in this Manual is organized into parts, as described in this section.

Part A, Introduction and Architecture Overview

Part A gives an overview of the Armv8-A and Armv9-A architecture profiles, including its relationship to the other

Arm PE architectures. It introduces the terminology used to describe the architecture, and gives an overview of the

Executions states, AArch64 and AArch32. It contains the following chapters:

Chapter A1 Introduction to the Arm Architecture

Read this for an introduction to the Arm architecture.

Chapter A2 Armv8-A Architecture Extensions

Read this for an introduction to the Armv8 architecture extensions.

Chapter A3 Armv9 Architecture Extensions

Read this for an introduction to the Armv9 architecture extensions.

Part B, The AArch64 Application Level Architecture

Part B describes the AArch64 state application level view of the architecture. It contains the following chapters:

Chapter B1 The AArch64 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.

Chapter B2 The AArch64 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64

state. It includes information about Arm memory types, attributes, and memory access controls.

Part C, The A64 Instruction Set

Part C describes the A64 instruction set, which is used in AArch64 state. It contains the following chapters:

Chapter C1 The A64 Instruction Set

Read this for a description of the A64 instruction set and common instruction operation details.

Chapter C2 About the A64 Instruction Descriptions

Read this to understand the format of the A64 instruction descriptions.

Chapter C3 A64 Instruction Set Overview

Read this for an overview of the A64 instructions.

Chapter C4 A64 Instruction Set Encoding

Read this for a description of the A64 instruction set encoding.

Chapter C5 The A64 System Instruction Class

Read this for a description of the AArch64 System instructions and register descriptions, and the

System instruction class encoding space.

Chapter C6 A64 Base Instruction Descriptions

Read this for information on key aspects of the A64 base instructions and for descriptions of the

individual instructions, which are listed in alphabetical order.

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