NXP LPC17xx 用户手册：ARM Cortex-M3 微控制器指南

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"NXP系列的LPC17xx手册，这是一本针对ARM学习的用户手册，涵盖了LPC1768、LPC1766、LPC1765等多个型号的微控制器，主要特性包括基于ARMCortex-M3内核的32位处理能力，以及集成的USB、以太网、CAN、I2S等功能。" LPC17xx系列是NXP半导体公司推出的一系列高性能、低功耗的微控制器，基于ARM的Cortex-M3内核，适用于各种嵌入式应用。该手册（UM10360）详细介绍了LPC17xx的硬件特性和功能，是开发者进行产品设计和系统集成的重要参考资料。 LPC17xx的特性包括： 1. **ARMCortex-M3内核**：提供高效的32位处理能力，适合实时操作系统的执行和复杂的控制任务。 2. **内存配置**：通常包含闪存、SRAM等存储资源，允许用户存储程序代码和数据。 3. **外设接口**：集成了多种通信接口，如USB主机和设备端口、以太网MAC、多个CAN（控制器局域网络）接口，以及I2S（集成电路声音）接口，方便连接各种外围设备。 4. **模拟和数字外设**：可能包含ADC（模数转换器）、DAC（数模转换器）、PWM（脉宽调制）单元等，满足不同应用场景的需求。 5. **电源管理**：具有低功耗模式，有助于在电池供电或能源受限的环境中优化能效。手册内容可能涵盖以下几个部分： - **概述**：介绍LPC17xx系列的基本架构和特性。 - **系统级描述**：详述内部总线结构、时钟系统、复位和中断系统。 - **外设描述**：每个内置外设的工作原理、配置和使用方法。 - **软件支持**：可能包括开发工具、固件库和示例代码的简介。 - **电路设计指南**：指导如何正确地将LPC17xx接入电路板并进行系统设计。 - **应用实例**：展示常见应用案例和设计考虑。 - **故障排查和问题解决**：提供遇到问题时的诊断和解决建议。手册的修订历史表明，这个版本（Rev.00.06）是2009年6月5日的初步修订版，之前经历了多次内部更新，意味着内容可能在不断优化和完善。在进行ARM学习和LPC17xx微控制器的项目开发时，这份手册是不可或缺的参考材料，它能帮助开发者深入理解LPC17xx的内部工作机制，有效利用其丰富的功能来实现高效、可靠的系统设计。

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1. Introduction

The system control block includes several system features and control registers for a

number of functions that are not related to specific peripheral devices. These include:

• Reset

• Brown-Out Detection

• External Interrupt Inputs

• Miscellaneous System Controls and Status

• Code Security vs. Debugging

Each type of function has its own register(s) if any are required and unneeded bits are

defined as reserved in order to allow future expansion. Unrelated functions never share

the same register addresses

2. Pin description

Table 3–6 shows pins that are associated with System Control block functions.

3. Register description

All registers, regardless of size, are on word address boundaries. Details of the registers

appear in the description of each function.

UM10360

Chapter 3: LPC17xx System control

Rev. 00.06 — 5 June 2009 User manual

Table 6. Pin summary

Pin name Pin

direction

Pin description

EINT0 Input External Interrupt Input 0 - An active low/high level or

falling/rising edge general purpose interrupt input. This pin may be

used to wake up the processor from Sleep, Deep-sleep, or

Power-down modes.

EINT1 Input

External Interrupt Input 1 - See the EINT0 description above.

EINT2 Input

External Interrupt Input 2 - See the EINT0 description above.

EINT3 Input

External Interrupt Input 3 - See the EINT0 description above.

RESET

Input External Reset input - A LOW on this pin resets the chip, causing

I/O ports and peripherals to take on their default states, and the

processor to begin execution at address 0x0000 0000.

Table 7. Summary of system control registers

Name Description Access Reset value Address

External Interrupts

EXTINT External Interrupt Flag Register R/W 0x00 0x400F C140

EXTMODE External Interrupt Mode register R/W 0x00 0x400F C148

EXTPOLAR External Interrupt Polarity Register R/W 0x00 0x400F C14C

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UM10360

Chapter 3: LPC17xx System control

On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset,

External reset, and Watchdog reset), the IRC starts up. After the IRC-start-up time

(maximum of 60 μs on power-up) and after the IRC provides a stable clock output, the

reset signal is latched and synchronized on the IRC clock. Then the following two

sequences start simultaneously:

1. The 2-bit IRC wake-up timer starts counting when the synchronized reset is

de-asserted. The boot code in the ROM starts when the 2-bit IRC wake-up timer times

out. The boot code performs the boot tasks and may jump to the flash. If the flash is

not ready to access, the Flash Accelerator will insert wait cycles until the flash is

ready.

2. The flash wake-up timer (9-bit) starts counting when the synchronized reset is

de-asserted. The flash wakeup-timer generates the 100 μs flash start-up time. Once it

times out, the flash initialization sequence is started, which takes about 250 cycles.

When it’s done, the Flash Accelerator will be granted access to the flash.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

Figure 3–5

shows an example of the relationship between the RESET, the IRC, and the

processor status when the LPC17xx starts up after reset. See Section 4–3.2 “

Main

oscillator” for start-up of the main oscillator if selected by the user code.

Fig 5. Example of start-up after reset

valid threshold

rocessor status

DD(REG)(3V3)

IRC status

RESET

GND

60 μs

1 μs; IRC stability count

boot time

boot code executing

user code

boot code

execution

finishes;

user code starts

IRC

starts

IRC

stable

supply ramp-up

time

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UM10360

Chapter 3: LPC17xx System control

4.1 Reset Source Identification Register (RSID - 0x400F C180)

This register contains one bit for each source of Reset. Writing a 1 to any of these bits

clears the corresponding read-side bit to 0. The interactions among the four sources are

described below.

5. Brown-out detection

The LPC17xx includes 2-stage monitoring of the voltage on the V

DD(REG)(3V3)

pins. If this

voltage falls below 2.9 V, the Brown-Out Detector (BOD) asserts an interrupt signal to the

Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt

Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor

the signal by reading the Raw Interrupt Status Register.

The second stage of low-voltage detection asserts Reset to inactivate the LPC17xx when

the voltage on the V

DD(REG)(3V3)

pins falls below 2.6 V. This Reset prevents alteration of

the flash as operation of the various elements of the chip would otherwise become

unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at

which point the Power-On Reset circuitry maintains the overall Reset.

Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event

loop to sense the condition.

Table 8. Reset Source Identification register (RSID - address 0x400F C180) bit description

Bit Symbol Description Reset

value

0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in

this register. But if another Reset signal (e.g., External Reset) remains

asserted after the POR signal is negated, then its bit is set. This bit is not

affected by any of the other sources of Reset.

See text

1 EXTR Assertion of the RESET

signal sets this bit. This bit is cleared by POR,

but is not affected by WDT or BOD reset.

See text

2 WDTR This bit is set when the Watchdog Timer times out and the WDTRESET

bit in the Watchdog Mode Register is 1. It is cleared by any of the other

sources of Reset.

See text

3 BODR This bit is set when the V

DD(REG)(3V3)

voltage reaches a level below

2.6 V.

If the V

DD(REG)(3V3)

voltage dips from 3.3 V to 2.5 V and recovers, the

BODR bit will be set to 1.

If the V

DD(REG)(3V3)

voltage dips from 3.3 V to 2.5 V and continues to

decline to the level at which POR is asserted (nominally 1 V), the BODR

bit is cleared.

If the V

DD(REG)(3V3)

voltage rises continuously from below 1 V to a level

above 2.6 V, the BODR will be set to 1.

This bit is not affected by External Reset nor Watchdog Reset.

Note: Only in the case where a reset occurs and the POR = 0, the

BODR bit indicates if the V

DD(REG)(3V3)

voltage was below 2.6 V or not.

See text

7:4 - Reserved, user software should not write ones to reserved bits. The

value read from a reserved bit is not defined.

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UM10360

Chapter 3: LPC17xx System control

But when Brown-Out Detection is enabled to bring the LPC17xx out of Power-down mode

(which is itself not a guaranteed operation -- see Section 4–8.7 “

Power Mode Control

the wake-up timer has completed its delay. In this case, the net result of the transient BOD

is that the part wakes up and continues operation after the instructions that set

Power-down mode, without any interrupt occurring and with the BOD bit in the RSID being

0. Since all other wake-up conditions have latching flags (see Section 3–6.2 “

External

Interrupt flag register (EXTINT - 0x400F C140)” and Section 27–6.2), a wake-up of this

type, without any apparent cause, can be assumed to be a Brown-Out that has gone

away.

6. External interrupt inputs

TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. In

addition, external interrupts have the ability to wake up the CPU from Power-down mode.

Refer to Section 4–8.8 “

Wake-up from Reduced Power Modes” for details.

6.1 Register description

The external interrupt function has four registers associated with it. The EXTINT register

contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level

and edge sensitivity parameters.

[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.

6.2 External Interrupt flag register (EXTINT - 0x400F C140)

When a pin is selected for its external interrupt function, the level or edge on that pin

(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in

this register. This asserts the corresponding interrupt request to the NVIC, which will

cause an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding

bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive

state.

Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling

wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise

event that was just triggered by activity on the EINT pin will not be recognized in future.

Table 9. External Interrupt registers

Name Description Access Reset

value

[1]

Address

EXTINT The External Interrupt Flag Register contains

interrupt flags for EINT0, EINT1, EINT2 and

EINT3. See Table 3–10

R/W 0x00 0x400F C140

EXTMODE The External Interrupt Mode Register controls

whether each pin is edge- or level-sensitive.

See Table 3–11

R/W 0x00 0x400F C148

EXTPOLAR The External Interrupt Polarity Register controls

which level or edge on each pin will cause an

interrupt. See Table 3–12

R/W 0x00 0x400F C14C

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