MT29F4 Flash 芯片手册详解：ONFI 1.0 协议、SLC 技术和异步 I/O 性能

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"MT29F4 Flash 芯片手册" 本资源摘要信息是关于镁光MT29F4型号Flash芯片的手册，涵盖了芯片的特性、组织结构、性能参数、命令集等方面的知识点。 **特性** MT29F4 Flash 芯片符合 OpenNAND Flash Interface (ONFI) 1.0 标准，采用 Single-Level Cell (SLC) 技术，具有高可靠性和长寿命。该芯片具有异步 I/O 性能，读取和编程速度快，适合用于存储和程序加载等应用场景。 **组织结构** MT29F4 Flash 芯片的组织结构包括页、块和平面三个层次。一页的大小为 2112 bytes（2048+64 bytes），一个块的大小为 64 页（128K+4K bytes），一个平面的大小为 2个块 x 2048 块 per 平面。芯片的总大小为 4Gb、8Gb 或 16Gb。 **性能参数** MT29F4 Flash 芯片的性能参数包括读取速度、编程速度和擦除速度。读取一页的时间为 25μs，编程一页的时间为 200μs，擦除一个块的时间为 700μs。 **命令集** MT29F4 Flash 芯片支持 ONFI NAND Flash 协议，包括基本命令和高级命令。基本命令包括读取、编程、擦除等操作，而高级命令包括编程页缓存模式、读取页缓存模式、一次编程模式、两平面命令、交叉die操作、读取唯一标识符、块锁定等。 **应用场景** MT29F4 Flash 芯片广泛应用于存储和程序加载等领域，例如在 Zynq 芯片程序加载中使用该芯片。用户可以根据需要选择合适的命令和模式来实现不同的应用场景。 **结论** MT29F4 Flash 芯片手册提供了该芯片的详细信息，包括特性、组织结构、性能参数、命令集等方面的知识点。用户可以通过学习和了解这些知识点来更好地使用该芯片，实现不同的应用场景。

Device and Array Organization

Figure 9: Array Organization – MT29F4G08 (x8)

Cache Register

Data Register

2048 blocks

per plane

4096 blocks

per device

1 block 1 block

DQ0

DQ7

1 page = (2K + 64 bytes)

1 block = (2K + 64) bytes x 64 pages

= (128K + 4K) bytes

1 plane = (128K + 4K) bytes x 2048 blocks

= 2112Mb

1 device = 2112Mb x 2 planes

= 4224Mb

Plane of

even-numbered blocks

(0, 2, 4, 6, ..., 4092, 4094)

Plane of

odd-numbered blocks

(1, 3, 5, 7, ..., 4093, 4095)

642048 64

2112 bytes2112 bytes

6464

2048

Table 2: Array Addressing – MT29F4G08 (x8)

Cycle I/07 I/06 I/05 I/04 I/03 I/02 I/01 I/00

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW CA11 CA10 CA9 CA8

Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Fifth LOW LOW LOW LOW LOW LOW BA17 BA16

Notes:

1. Block address concatenated with page address = actual page address. CAx = column ad-

dress; PAx = page address; BAx = block address.

2. If CA11 is 1, then CA[10:6] must be 0.

3. BA6 controls plane selection.

Micron Confidential and Proprietary

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Device and Array Organization

PDF: 09005aef83b25735

m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 6: Asynchronous Interface Mode Selection

Mode

CE# CLE ALE WE# RE# I/Ox WP#

Standby

H X X X X X 0V/V

Command input L H L H X H

Address input L L H H X H

Data input L L L H X H

Data output L L L H X X

Write protect X X X X X X L

Notes:

1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V

or V

2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are

accepted by die (LUNs) even when they are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

Micron Confidential and Proprietary

4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory

Asynchronous Interface Bus Operation

PDF: 09005aef83b25735

m60a_4gb_8gb_16gb_ecc_nand.pdf - Rev. N 10/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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