DP83867IR：超低延迟千兆以太网PHY收发器，适用于TSN网络

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"DP83867IR是一款高性能、低功耗的千兆位以太网PHY收发器，适用于各种工业和网络应用。它提供了超低的RGMII延迟，TX小于90ns，RX小于290ns，符合时间敏感网络（TSN）标准，具有出色的抗静电放电保护能力，满足EN55011 Class B的发射标准，并且具备多种可编程功能，如RGMII延迟模式、集成MDI终端电阻和MDI/GMII/RGMII终端阻抗等。此外，它还支持WoL（Wake-on-LAN）包检测、25-MHz或125-MHz同步时钟输出、IEEE 1588时间戳的帧起始检测以及RJ45镜像模式。该器件完全符合IEEE 802.3的10BASE-T、100BASE-TX和1000BASE-T规范，提供线缆诊断功能，并兼容MII、GMII和RGMII MAC接口，支持不同电压配置，并内置JTAG支持。DP83867常用于电机驱动、工业自动化、现场总线支持、工业嵌入式计算、有线和无线通信基础设施、测试测量设备以及消费电子等多个领域。" DP83867IR千兆位以太网PHY收发器是德州仪器（TI）推出的一款高效能、高免疫力的网络物理层传输设备，专为满足现代工业网络和自动化系统的需求而设计。其关键特性包括： 1. 超低RGMII延迟：在传输（TX）和接收（RX）方面，DP83867IR实现了小于90ns和小于290ns的极低延迟，这对于实时数据传输和时间敏感网络应用至关重要。 2. 时间敏感网络（TSN）合规性：TSN允许在传统以太网架构中实现精确的时间同步和低延迟通信，对于工业自动化和实时通信场景非常关键。 3. 低功耗：457毫瓦的低功耗设计使得DP83867IR适合于能源效率要求高的应用。 4. 高ESD保护：超过8000V的IEC 61000-4-2静电放电保护等级，确保了设备在恶劣环境中的可靠性。 5. 辐射发射标准：符合EN55011 Class B标准，意味着在电磁兼容性方面表现出色，可以用于多种工业和家用环境。 6. 可编程RGMII延迟模式：16种不同的RX/TX延迟模式可调，增强了灵活性，适应不同网络配置需求。 7. 集成MDI终止电阻和可编程终端阻抗：简化了系统设计，同时保持信号完整性。 8. WoL（Wake-on-LAN）功能：支持通过特定的网络包唤醒系统，提高了能效管理。 9. 同步时钟输出：25-MHz或125-MHz的时钟输出选项，满足不同系统时钟同步需求。 10. 帧起始检测：用于IEEE 1588时间戳的精确计时，对于网络同步至关重要。 11. RJ45镜像模式：允许数据在多个端口间镜像，方便监控和故障排查。 12. 兼容性与线缆诊断：全面支持10BASE-T、100BASE-TX和1000BASE-T标准，并具备线缆诊断功能，确保连接质量。 13. 多样化的MAC接口选项：MII、GMII和RGMII，适应不同的系统接口需求。 14. 可配置的I/O电压：支持3.3V、2.5V和1.8V，便于与不同电压等级的系统兼容。 15. 快速链路断开模式：快速响应链路状态变化，提高系统的响应速度。 16. JTAG支持：通过JTAG接口进行调试和固件更新，简化维护流程。这些特性使得DP83867IR成为从电机驱动到消费电子，再到通信基础设施的广泛应用的理想选择，它的高稳定性和灵活性使其在工业4.0时代扮演着重要的角色。

7.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Operating junction temperature

Commercial (DP83867CRRGZ) 0 90 °C

Industrial (DP83867IRRGZ)

–40 105 °C

Industrial (DP83867IRPAP)

7.4 Thermal Information

THERMAL METRIC

(1)

DP83867IR DP83867IR,

DP83867CR

UNIT

PAP (HTQFP) RGZ (QFN)

64 PINS 48 PINS

θJA

Junction-to-ambient thermal resistance 30.9 30.8 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 13.6 18.7 °C/W

θJC(bot)

Junction-to-case (bottom) thermal resistance 0.9 1.4 °C/W

θJB

Junction-to-board thermal resistance 15.6 7.5 °C/W

Junction-to-top characterization parameter 0.4 0.3 °C/W

Junction-to-board characterization parameter 15.5 7.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These

specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life

of the product containing it.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

3.3-V V

DDIO

High level output voltage I

= –4 mA 2 V

Low level output voltage I

= 4 mA 0.6 V

High level input voltage 1.7 V

Low level input voltage 0.7 V

2.5-V V

VDDIO

High level output voltage I

= –4 mA V

DDIO

× 0.8 V

Low level output voltage I

= 4 mA 0.6 V

High level input voltage 1.7 V

Low level input voltage 0.7 V

1.8-V V

DDIO

High level output voltage I

= –1 mA V

DDIO

– 0.2 V

Low level output voltage I

= 1 mA 0.2 V

High level input voltage 0.7 × V

DDIO

Low level input voltage 0.2 × VDDIO V

XI INPUT VOLTAGE

OSC

Input voltage for 25 MHz

Oscillator

1.5 1.9 Vpp

High level input voltage 1.4 V

Low level input voltage 0.45 V

DC CHARACTERISTICS

DP83867IR, DP83867CR

SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022

www.ti.com

16 Submit Document Feedback

Product Folder Links: DP83867IR DP83867CR

7.7 Reset Timing

See Figure 7-14.

PARAMETER TEST CONDITIONS

(1)

MIN NOM MAX UNIT

Post RESET stabilization time prior to MDC

preamble for register accesses

MDIO is pulled high for 32-bit serial

management initialization.

MDC may toggle during this period when

MDIO remains high.

195 µs

T2 Hardware configuration latch-in time from the

deassertion of RESET (either soft or hard)

Hardware Configuration Pins are

described in Section 8.5.1.

120 ns

T3 Hardware configuration pins transition to

output drivers

64 ns

RESET pulse width

X1 Clock must be stable for a minimum of

1 μs during RESET pulse low time

1 µs

(1) Ensured by production test, characterization, or design.

7.8 MII Serial Management Timing

See Figure 7-15.

PARAMETER TEST CONDITIONS

(1)

MIN NOM MAX UNIT

T1 MDC to MDIO (output) delay time 0 10 ns

T2 MDIO (input) to MDC setup time 10 ns

T3 MDIO (input) to MDC hold time 10 ns

T4 MDC frequency 2.5 25 MHz

(1) Ensured by production test, characterization, or design.

7.9 RGMII Timing

See Figure 7-16 and .Figure 7-17

PARAMETER TEST CONDITIONS

(5)

MIN NOM MAX UNIT

skewT

Data to Clock output Skew

(at Transmitter)

See

(1)

–500 0 500 ps

skewR

Data to Clock input Skew

(at Receiver)

See

(1)

1 1.8 2.6 ns

setupT

Data to Clock output Setup

(at Transmitter – internal delay)

See

(4)

1.2 2 ns

holdT

Clock to Data output Hold

(at Transmitter – internal delay)

See

(4)

1.2 2 ns

setupR

Data to Clock input Setup

(at Reciever – internal delay)

See

(4)

1 2 ns

holdR

Clock to Data input Hold

(at Receiver – internal delay)

See

(4)

1 2 ns

cyc

Clock Cycle Duration See

(2)

7.2 8 8.8 ns

Duty_G Duty Cycle for Gigabit See

(3)

(7)

45 50 55%

Duty_T Duty Cycle for 10/100T See

(3)

(7)

40 50 60%

Rise Time (20% to 80%) 0.75 ns

Fall Time (20% to 80%) 0.75 ns

TXLAT

RGMII to MDI Latency See

(6)

88 ns

RXLAT

MDI to RGMII Latency See

(6)

288 ns

(1) When operating without RGMII internal delay, the PCB design requires clocks to be routed such that an additional trace delay of

greater than 1.5 ns is added to the associated clock signal.

(2) For 10-Mbps and 100-Mbps, Tcyc will scale to 400 ns ± 40 ns and 40 ns ± 4 ns.

(3) Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as

minimum duty cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.

(4) Device may operate with or without internal delay.

www.ti.com

DP83867IR, DP83867CR

SNLS484G – FEBRUARY 2015 – REVISED OCTOBER 2022

Submit Document Feedback

Product Folder Links: DP83867IR DP83867CR

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