"TI-DS64BR401.pdf: 以太网转接驱动器和信号调节设备"

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The TI-DS64BR401.pdf is a document that describes the features and specifications of the DS64BR401 Quad Bi-Directional Repeater with Equalization and De-Emphasis. This device is designed to be used as a quad lane bi-directional signal conditioning repeater for 6.0/3.0/1.5 Gbps SATA/SAS and other high-speed bus applications with data rates up to 6.4 Gbps. It provides signal conditioning on both input and output for extended reach and equalization. The DS64BR401 is capable of bi-directional repeating at rates of up to 6.4 Gbps, making it suitable for a wide range of high-speed applications. It is designed to provide signal conditioning on both the input and output sides, allowing for improved signal integrity and extended reach. The device also includes equalization and de-emphasis features, further enhancing its ability to handle high-speed data transmission. One of the key features of the DS64BR401 is its ability to provide signal conditioning for up to 6.4 Gbps data rates. This makes it suitable for use in a variety of high-speed applications, including SATA/SAS and other bus systems. The device is capable of bi-directional repeating, allowing for efficient data transmission in both directions. It also includes equalization and de-emphasis capabilities, further improving the integrity of the transmitted signals. Overall, the DS64BR401 is a high-performance quad lane bi-directional repeater that is well-suited for high-speed data transmission applications. Its signal conditioning, equalization, and de-emphasis features make it a versatile and reliable choice for a wide range of high-speed bus systems. With its ability to handle data rates of up to 6.4 Gbps and provide extended reach, the DS64BR401 is an excellent option for applications requiring robust and high-quality signal transmission.

DS64BR401

www.ti.com

SNLS304G –JUNE 2009–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS

Over recommended operating supply and temperature ranges with default register settings unless other specified.

(1)

Symbol Parameter Conditions Min Typ Max Units

POWER

PD Power Dissipation PWDN = 0,

EQx = 0, DEMx = 0 dB,

758 950 mW

K28.5 pattern

VOD = 1.0 Vp-p

PWDN = 1, ENSMB = 0 0.92 1.125 mW

LVCMOS / LVTTL DC SPECIFICATIONS

High Level Input Voltage 2.0 3.6 V

Low Level Input Voltage 0 0.8 V

Input High Current V

= 3.3V,

-15 +15 μA

Inputs OPEN: SDA, SCL, PWDN

= 3.3V,

Inputs with PULL-DOWN -15 +120 uA

and FLOAT — mid level

Input Low Current V

= 0V,

Inputs OPEN: SDA, SCL, PWDN and with -15 +15 μA

PULL-DOWN

= 0V,

-80 +15 uA

Inputs with FLOAT — mid level

CML RECEIVER INPUTS (IN_n+, IN_n-)

RX-DIFF

Rx Differential Return Loss 150 MHz – 1.5 GHz -20

(SDD11),

150 MHz – 3.0 GHz -13.5 dB

(2)

150 MHz – 6.0 GHz -8

RX-CM

Rx Common Mode Input 150 MHz – 3.0 GHz,

(2)

-10 dB

Return Loss (SCC11)

RX-IB

Rx Impedance Balance 150 MHz – 3.0 GHz,

(2)

-27 dB

(SDC11)

Maximum current allowed at

−30 +30 mA

IN+ or IN- input pin.

Input Resistance Single ended to V

(2)

50 Ω

ITD

Input Differential Impedance DC tested,

(2)

between 85 100 115 Ω

IN+ and IN-

ITIB

Input Differential Impedance DC tested,

(2)

5 Ω

Imbalance

ICM

Input Common Mode DC tested,

(2)

20 25 35 Ω

Impedance

RX-DIFF

Differential Rx peak to peak DC voltage,

0.1 1.2 V

voltage SD_TH = 20 kΩ to GND

RX-SD_TH

Electrical Idle detect SD_TH = Float,

(3)

,Figure 6

40 175 mVp-p

threshold (differential)

LPDS OUTPUTS (OUT_n+, OUT_n-)

Output Voltage Swing R

= 50 Ω ±1% to GND (AC coupled with 10

nF), 6.4 Gbps,

(4)

500 600 700 mV

P-P

DEMx = 0 dB,

VOD[1:0] = 00

VOD[1:0] = 11 1100 1265 1450 mV

P-P

(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwise

modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not

verified.

(2) Typical values represent most likely parametric norms at V

= 2.5V, T

= 25°C., and at the Recommended Operation Conditions at the

time of product characterization and are not verified.

(3) Measured at package pins of receiver. The 130 mVp-p is a typical threshold level and does not include hysteresis, thus less than 40

mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with resistor to GND overrides this default setting.

(4) Measured with clock-like {11111 00000} pattern.

Product Folder Links: DS64BR401

DS64BR401

SNLS304G –JUNE 2009–REVISED APRIL 2013

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating supply and temperature ranges with default register settings unless other specified.

(1)

Symbol Parameter Conditions Min Typ Max Units

OCM

Output Common-Mode Single-ended measurement DC-Coupled with

–

Voltage 50Ω termination, V

1.4

(2)

TX-RF

Transmitter Rise/ Fall Time 20% to 80% of differential output voltage,

measured within 1” from output pins, 67 85 ps

(2) (4)

, Figure 2

RF-DELTA

Tx rise/fall mismatch 20% to 80% of differential output voltage,

(2)

0.1 UI

(4)

TX-DIFF

Tx Differential Return Loss Repeating 1100b (D24.3) pattern,

(SDD22), VOD = 1.0 Vp-p, -11

(2)

150 MHz – 1.5 GHz

150 MHz – 3.0 GHz -10

150 MHz – 6.0 GHz -5

TX-CM

Tx Common Mode Return Repeating 1100b (D24.3) pattern,

Loss VOD = 1.0 Vp-p,

(2)

-10 dB

(SCC22) 50 MHz – 3.0 GHz

TX-IB

Tx Impedance Balance Repeating 1100b (D24.3) pattern,

(SDC22) VOD = 1.0 Vp-p,

(2)

-30 dB

50 MHz – 3.0 GHz

TX-SHORT

Tx Output Short Circuit OA/B_n = GND

90 mA

Current Limit

OTD

Output Differential DC tested,

(5)

Impedance between OUT+ 85 100 125 Ω

and OUT-

OTIB

Output Differential DC tested,

(5)

5 Ω

Impedance Imbalance

OCM

Output Common Mode DC tested,

(5)

20 25 35 Ω

Impedance

TX-CM-DELTA

Common Mode Voltage

(6)

Delta between active burst

±40 mV

and electrical Idle of an

OOB signal

Max time to transition to VIN = 800 mVp-p, repeating 1100b (D24.3)

valid electrical idle after pattern at 3 Gbps,

6.5 9.5 ns

leaving active burst in OOB SD_TH = Float, Figure 4

signaling

Max time to transition to VIN = 800 mVp-p, repeating 1100b (D24.3)

valid active burst after pattern at 3 Gbps,

5.5 8 ns

leaving idle in OOB SD_TH = Float, Figure 4

signaling

Differential Propagation Propagation delay measured at midpoint

Delay (Low to High and High crossing between input to output, Figure 3, 150 200 250 ps

to Low Edge) EQx[1:0] = 11, DEMx[1:0] = −6 dB

EQx[1:0] = OFF, DEMx[1:0] = 0 dB 120 170 220 ps

LSK

Lane to Lane Skew in a V

= 2.5 V, T

= 25°C

27 ps

Single Part

PPSK

Part to Part Propagation V

= 2.5 V, T

= 25°C

35 ps

Delay Skew

EQUALIZATION

DJ1 Residual Deterministic Jitter Tx Launch Amplitude = 0.8 to

at 6.4 Gbps 1.2 Vp–p, 40” 4–mil FR4 trace,

EQx[1:0] = 0F, DEMx[1:0] = 0 dB, 0.12 0.25 UI

P-P

VOD = 1.0 Vp-p, K28.5,

SD_TH = float,

(5)

(5) Typical values represent most likely parametric norms at V

= 2.5V, T

= 25°C., and at the Recommended Operation Conditions at the

time of product characterization and are not verified.

(6) Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.VCM

= (A + B) / 2, A = OUT+, B = OUT-.

Product Folder Links: DS64BR401

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