TI Tiva TM4C1294NCPDT微控制器数据手册

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"TI 电赛M4核tm4c1294ncpdt芯片手册" TI的Tiva TM4C1294NCPDT微控制器是一款高性能、低功耗的微控制器，专为嵌入式应用设计，广泛应用于电子竞赛如四川省电赛TI杯。这款芯片基于ARM Cortex-M4内核，提供了强大的处理能力和浮点运算单元（FPU），使其在实时控制和信号处理任务中表现出色。该手册详细介绍了TM4C1294NCPDT的特性，包括其硬件结构、功能配置、外设接口以及编程模型。以下是一些关键知识点： 1. **ARM Cortex-M4内核**：Cortex-M4是ARM公司的一款高效能、低功耗的32位处理器内核，支持单指令周期的浮点运算，适用于要求实时性能的应用。 2. **集成的外设**：TM4C1294NCPDT集成了丰富的外设，如GPIO（通用输入/输出）、UART（通用异步收发传输器）、SPI（串行外围接口）、I2C（仪表总线）、CAN（控制器局域网络）、以太网MAC、USB主机/设备接口等，方便用户进行系统扩展和通信。 3. **内存配置**：该芯片通常包含闪存和SRAM存储器，用于程序存储和数据处理。闪存用于存储固件，而SRAM则提供高速的数据访问。 4. **模拟功能**：Tiva系列微控制器通常配备有ADC（模数转换器）、DAC（数模转换器）和其他模拟电路，适用于混合信号应用。 5. **电源管理**：TI的Tiva系列芯片具有高效的电源管理模块，可实现动态电压和频率调整，以优化能源效率。 6. **开发工具与生态系统**：TI提供TivaWare软件库，这是一个针对Tiva系列MCU的开源软件框架，包含驱动程序、例程和应用示例，便于开发者快速进行系统开发。 7. **调试支持**：TM4C1294NCPDT支持JTAG和SWD（串行线调试）接口，允许通过标准的嵌入式调试工具进行程序调试和故障排查。 8. **生产数据与质量保证**：TI提供标准质保，并指出产品符合规格书中的参数。但生产过程并不保证测试所有参数，因此在关键应用中使用时，用户需要根据自身需求进行额外测试。 9. **出口通知**：由于TI产品可能包含受管制的技术，手册中包含了出口通知，提醒接收者遵守相关的出口法规。 TI的TM4C1294NCPDT微控制器因其强大的处理能力、丰富的外设和易用的开发环境，成为许多电子竞赛和嵌入式项目中的首选平台。对于参赛者或开发者来说，深入理解和掌握该芯片的手册内容至关重要，能够有效提升项目的成功可能性和效率。

Figure 27-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1868

Figure 27-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1868

Figure 27-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1869

Figure 27-33. I

C Timing ....................................................................................................... 1870

Figure 27-34. MOSC Crystal Characteristics for Ethernet ........................................................ 1871

Figure 27-35. Single-Ended MOSC Characteristics for Ethernet .............................................. 1872

Figure 27-36. Reset Timing ................................................................................................... 1872

Figure 27-37. 100 Base-TX Transmit Timing ........................................................................... 1873

Figure 27-38. 10Base-TX Normal Link Pulse Timing ............................................................... 1873

Figure 27-39. Auto-Negotiation Fast Link Pulse Timing ........................................................... 1874

Figure 27-40. 100Base-TX Signal Detect Timing ..................................................................... 1874

Figure 27-41. ULPI Interface Timing Diagram ......................................................................... 1876

Figure A-1. Key to Part Numbers ........................................................................................ 1885

Figure A-2. TM4C1294NCPDT 128-Pin TQFP Package Diagram ......................................... 1887

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Table of Contents

List of Tables

Table 1. Revision History .................................................................................................. 45

Table 2. Documentation Conventions ................................................................................ 49

Table 1-1. TM4C1294NCPDT Microcontroller Features .......................................................... 52

Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 85

Table 2-2. Processor Register Map ....................................................................................... 86

Table 2-3. PSR Register Combinations ................................................................................. 92

Table 2-4. Memory Map ..................................................................................................... 103

Table 2-5. Memory Access Behavior ................................................................................... 107

Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 109

Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 109

Table 2-8. Exception Types ................................................................................................ 115

Table 2-9. Interrupts .......................................................................................................... 116

Table 2-10. Exception Return Behavior ................................................................................. 123

Table 2-11. Faults ............................................................................................................... 124

Table 2-12. Fault Status and Fault Address Registers ............................................................ 125

Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 127

Table 3-1. Core Peripheral Register Regions ....................................................................... 134

Table 3-2. Memory Attributes Summary .............................................................................. 138

Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 140

Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 141

Table 3-5. AP Bit Field Encoding ........................................................................................ 141

Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 142

Table 3-7. QNaN and SNaN Handling ................................................................................. 145

Table 3-8. Peripherals Register Map ................................................................................... 146

Table 3-9. Interrupt Priority Levels ...................................................................................... 171

Table 3-10. Example SIZE Field Values ................................................................................ 199

Table 4-1. JTAG_SWD_SWO Signals (128TQFP) ............................................................... 208

Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 210

Table 4-3. JTAG Instruction Register Commands ................................................................. 216

Table 5-1. System Control & Clocks Signals (128TQFP) ...................................................... 220

Table 5-2. Reset Sources ................................................................................................... 221

Table 5-3. Clock Source Options ........................................................................................ 231

Table 5-4. Clock Source State Following POR ..................................................................... 231

Table 5-5. System Clock Frequency ................................................................................... 235

Table 5-6. System Divisor Factors for f

vco

=480 MHz ............................................................ 237

Table 5-7. Actual PLL Frequency ........................................................................................ 238

Table 5-8. Peripheral Memory Power Control ...................................................................... 243

Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 244

Table 5-10. MOSC Configurations ........................................................................................ 247

Table 5-11. System Control Register Map ............................................................................. 247

Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 277

Table 5-13. MOSC Configurations ........................................................................................ 281

Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 300

Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 303

Table 5-16. Module Power Control ........................................................................................ 451

Table 5-17. Module Power Control ........................................................................................ 453

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TM4C1294NCPDT Microcontroller

Table 5-18. Module Power Control ........................................................................................ 456

Table 5-19. Module Power Control ........................................................................................ 461

Table 5-20. Module Power Control ........................................................................................ 463

Table 5-21. Module Power Control ........................................................................................ 465

Table 5-22. Module Power Control ........................................................................................ 467

Table 5-23. Module Power Control ........................................................................................ 470

Table 5-24. Module Power Control ........................................................................................ 472

Table 5-25. Module Power Control ........................................................................................ 476

Table 5-26. Module Power Control ........................................................................................ 478

Table 5-27. Module Power Control ........................................................................................ 480

Table 5-28. Module Power Control ........................................................................................ 482

Table 5-29. Module Power Control ........................................................................................ 484

Table 5-30. Module Power Control ........................................................................................ 486

Table 5-31. Module Power Control ........................................................................................ 488

Table 5-32. Module Power Control ........................................................................................ 490

Table 5-33. Module Power Control ........................................................................................ 492

Table 5-34. Module Power Control ........................................................................................ 494

Table 6-1. System Exception Register Map ......................................................................... 523

Table 7-1. Hibernate Signals (128TQFP) ............................................................................. 534

Table 7-2. HIB Clock Source Configurations ........................................................................ 535

Table 7-3. Hibernation Module Register Map ....................................................................... 552

Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 605

Table 8-2. Flash Memory Protection Policy Combinations .................................................... 610

Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 614

Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 617

Table 8-5. Master Memory Access Availability ..................................................................... 621

Table 8-6. Flash Register Map ............................................................................................ 622

Table 9-1. μDMA Channel Assignments .............................................................................. 680

Table 9-2. Request Type Support ....................................................................................... 682

Table 9-3. Control Structure Memory Map ........................................................................... 684

Table 9-4. Channel Control Structure .................................................................................. 684

Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 693

Table 9-6. μDMA Interrupt Assignments .............................................................................. 694

Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 695

Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 696

Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 697

Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 697

Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 699

Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 699

Table 9-13. μDMA Register Map .......................................................................................... 701

Table 10-1. GPIO Pins With Special Considerations .............................................................. 743

Table 10-2. GPIO Pins and Alternate Functions (128TQFP) ................................................... 743

Table 10-3. GPIO Drive Strength Options .............................................................................. 753

Table 10-4. GPIO Pad Configuration Examples ..................................................................... 754

Table 10-5. GPIO Interrupt Configuration Example ................................................................ 755

Table 10-6. GPIO Pins With Special Considerations .............................................................. 756

Table 10-7. GPIO Register Map ........................................................................................... 757

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Table 10-8. GPIO Pins With Special Considerations .............................................................. 770

Table 10-9. GPIO Pins With Special Considerations .............................................................. 776

Table 10-10. GPIO Pins With Special Considerations .............................................................. 778

Table 10-11. GPIO Pins With Special Considerations .............................................................. 781

Table 10-12. GPIO Pins With Special Considerations .............................................................. 787

Table 10-13. GPIO Drive Strength Options .............................................................................. 800

Table 11-1. External Peripheral Interface Signals (128TQFP) ................................................. 817

Table 11-2. EPI Interface Options ......................................................................................... 822

Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 823

Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 827

Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 828

Table 11-6. Chip Select Configuration Register Assignment ................................................... 829

Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 829

Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 831

Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 833

Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 838

Table 11-11. Data Phase Wait State Programming .................................................................. 843

Table 11-12. EPI General-Purpose Signal Connections ........................................................... 849

Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 854

Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 880

Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 886

Table 12-1. Endian Configuration ......................................................................................... 947

Table 12-2. Endian Configuration with Bit Reversal ................................................................ 947

Table 12-3. CCM Register Map ............................................................................................ 949

Table 13-1. Available CCP Pins ............................................................................................ 956

Table 13-2. General-Purpose Timers Signals (128TQFP) ....................................................... 957

Table 13-3. General-Purpose Timer Capabilities .................................................................... 958

Table 13-4. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 960

Table 13-5. 16-Bit Timer With Prescaler Configurations ......................................................... 961

Table 13-6. Counter Values When the Timer is Enabled in RTC Mode .................................... 962

Table 13-7. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 963

Table 13-8. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 964

Table 13-9. Counter Values When the Timer is Enabled in PWM Mode ................................... 966

Table 13-10. Timeout Actions for GPTM Modes ...................................................................... 969

Table 13-11. Timers Register Map .......................................................................................... 974

Table 14-1. Watchdog Timers Register Map ........................................................................ 1031

Table 15-1. ADC Signals (128TQFP) .................................................................................. 1055

Table 15-2. Samples and FIFO Depth of Sequencers .......................................................... 1056

Table 15-3. Sample and Hold Width in ADC Clocks ............................................................. 1058

Table 15-4. R

and F

CONV

Values with Varying N

Values and F

ADC

= 16 MHz ..................... 1059

Table 15-5. R

and F

CONV

Values with Varying N

Values and F

ADC

= 32 MHz ..................... 1059

Table 15-6. Differential Sampling Pairs ............................................................................... 1066

Table 15-7. ADC Register Map ........................................................................................... 1073

Table 15-8. Sample and Hold Width in ADC Clocks ............................................................. 1127

Table 15-9. Sample and Hold Width in ADC Clocks ............................................................. 1139

Table 15-10. Sample and Hold Width in ADC Clocks ............................................................. 1147

Table 16-1. UART Signals (128TQFP) ................................................................................ 1163

Table 16-2. Flow Control Mode ........................................................................................... 1169

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Table 16-3. UART Register Map ......................................................................................... 1173

Table 17-1. SSI Signals (128TQFP) .................................................................................... 1228

Table 17-2. QSSI Transaction Encodings ............................................................................ 1231

Table 17-3. SSInFss Functionality ...................................................................................... 1231

Table 17-4. Legacy Mode TI, Freescale SPI Frame Format Features .................................... 1233

Table 17-5. SSI Register Map ............................................................................................. 1243

Table 18-1. I2C Signals (128TQFP) .................................................................................... 1277

Table 18-2. Examples of I

C Master Timer Period Versus Speed Mode ................................. 1284

Table 18-3. Examples of I

C Master Timer Period in High-Speed Mode ................................ 1285

Table 18-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1300

Table 18-5. Write Field Decoding for I2CMCS[6:0] ............................................................... 1308

Table 19-1. Controller Area Network Signals (128TQFP) ...................................................... 1357

Table 19-2. Message Object Configurations ........................................................................ 1363

Table 19-3. CAN Protocol Ranges ...................................................................................... 1371

Table 19-4. CANBIT Register Values .................................................................................. 1371

Table 19-5. CAN Register Map ........................................................................................... 1375

Table 20-1. Ethernet Signals (128TQFP) ............................................................................. 1409

Table 20-2. Enhanced Transmit Descriptor 0 (TDES0) ......................................................... 1414

Table 20-3. Enhanced Transmit Descriptor 1 (TDES1) ......................................................... 1417

Table 20-4. Enhanced Transmit Descriptor 2 (TDES2) ......................................................... 1418

Table 20-5. Enhanced Transmit Descriptor 3 (TDES3) ......................................................... 1418

Table 20-6. Enhanced Transmit Descriptor 6 (TDES6) ......................................................... 1418

Table 20-7. Enhanced Transmit Descriptor 7 (TDES7) ......................................................... 1418

Table 20-8. Enhanced Receive Descriptor 0 (RDES0) .......................................................... 1419

Table 20-9. RDES0 Checksum Offload bits ......................................................................... 1421

Table 20-10. Enhanced Receive Descriptor 1 (RDES1) .......................................................... 1422

Table 20-11. Enhanced Receive Descriptor 2 (RDES2) .......................................................... 1422

Table 20-12. Enhanced Receive Descriptor 3 (RDES3) .......................................................... 1422

Table 20-13. Enhanced Received Descriptor 4 (RDES4) ........................................................ 1422

Table 20-14. Enhanced Receive Descriptor 6 (RDES6) .......................................................... 1424

Table 20-15. Enhanced Receive Descriptor 7 (RDES7) .......................................................... 1424

Table 20-16. TX MAC Flow Control ...................................................................................... 1437

Table 20-17. RX MAC Flow Control ...................................................................................... 1437

Table 20-18. VLAN Match Status .......................................................................................... 1450

Table 20-19. CRC Replacement Based on Bit 27 and Bit 24 of TDES0 ................................... 1452

Table 20-20. Forced Mode Configurations ............................................................................. 1458

Table 20-21. Advertised Mode Configurations ....................................................................... 1459

Table 20-22. EMACPC to PHY Register Mapping .................................................................. 1465

Table 20-23. Ethernet Register Map ..................................................................................... 1467

Table 20-24. PPSCTRL Bit Field Values ............................................................................... 1549

Table 21-1. USB Signals (128TQFP) .................................................................................. 1646

Table 21-2. List of Registers ............................................................................................... 1647

Table 22-1. Analog Comparators Signals (128TQFP) ........................................................... 1654

Table 22-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1656

Table 22-3. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1657

Table 22-4. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1658

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