LM27966
SNVS448B –JULY 2006–REVISED MAY 2013
www.ti.com
Electrical Characteristics
(1)(2)
Limits in standard typeface are for T
J
= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: V
IN
= 3.6V; V
RESET
= V
IN
; VIO = 1.8V V
Dx
= 0.4V; V
D
AUX
= 0.4V; R
SET
= 16.9kΩ; D
x
= D
AUX
=
Fullscale Current; EN-MAIN, EN-D5 Bits = “1”; C1=C2=1.0µF, C
IN
=C
OUT
=1.0µF; Specifications related to output current(s) and
current setting pins (I
Dx
and I
SET
) apply to Main Display and Auxiliary LED.
(3)
Parameter Test Conditions Min Typ Max Units
3.0V ≤ V
IN
≤ 5.5V mA
18.2 (-9.5%) 20.1 22.0 (+9.5%)
EN-AUX= '0' (%)
Output Current Regulation
Main Display or Auxiliary LED Enabled
3.0V ≤ V
IN
≤ 5.5V mA
19.2 (-7.7%) 20.8 22.4 (+7.7%)
EN-AUX = '1' and EN-MAIN = EN-D5 = '0' (%)
I
Dx
30
3.2V ≤ V
IN
≤ 5.5V
Maximum Output Current Regulation
Dx
R
SET
= 8.33kΩ
Main Display and Auxiliary LED Enabled mA
V
LED
= 3.6V
30
(4)
EN-MAIN = EN-D5 = EN-AUX = “1”
D
AUX
I
Dx-MATCH
LED Current Matching
(5)
0.3 1.7 %
Gain = 3/2 2.75
Open-Loop Charge Pump Output
R
OUT
Ω
Resistance
Gain = 1 1
V
Dx
Falling
V
DxTH
V
Dx
1x to 3/2x Gain Transition Threshold 175 mV
RSET = 16.9kΩ
I
Dxx
= 95% ×I
Dxx
(nom.)
Current Source Headroom Voltage
(I
Dxx
(nom) ≈ 15mA)
V
HR
Requirement 110 mV
Gain = 3/2
(6)
EN-MAIN = EN-D5 and/or EN-AUX= "1"
I
Q
Quiescent Supply Current Gain = 1.5x, No Load 2.90 3.32 mA
I
SD
Shutdown Supply Current All EN-x bits = "0" 3.4 5.4 µA
V
SET
I
SET
Pin Voltage 2.7V ≤ V
IN
≤ 5.5V 1.25 V
I
Dx/
Output Current to Current Set Ratio Main
200
I
SET
Display, DAUX
f
SW
Switching Frequency 0.89 1.27 1.57 MHz
t
START
Start-up Time P
OUT
= 90% steady state 250 µs
f
PWM
Internal Diode Current PWM Frequency 20 kHz
Reset 0 0.45
V
RESET
Reset Voltage Thresholds 2.7V ≤ V
IN
≤ 5.5V V
Normal Operation 1.2 V
IN
I
2
C Compatible Interface Voltage Specifications (SCL, SDIO, VIO)
V
IO
Serial Bus Voltage Level 2.7V ≤ V
IN
≤ 5.5V
(7)
1.4 V
IN
V
V
IL
Input Logic Low "0" 2.7V ≤ V
IN
≤ 5.5V, VIO = 3.0V 0 0.3 × V
IO
V
V
IH
Input Logic High "1" 2.7V ≤ V
IN
≤ 5.5V, VIO = 3.0V 0.7 × V
IO
V
IO
V
V
OL
Output Logic Low "0" I
LOAD
= 3mA 400 mV
I
2
C Compatible Interface Timing Specifications (SCL, SDIO, VIO)
(8)
t
1
SCL (Clock Period) 2.5 µs
t
2
Data In Setup Time to SCL High 100 ns
t
3
Data Out stable After SCL Low 0 ns
t
4
SDIO Low Setup Time to SCL Low (Start) 100 ns
SDIO High Hold Time After SCL High
t
5
100 ns
(Stop)
(1) All voltages are with respect to the potential at the GND pin.
(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most
likely norm.
(3) C
IN
, C
POUT
, C
1
, and C
2
: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics
(4) The maximum total output current for the LM27966 should be limited to 180mA. The total output current can be split among any of the
three banks (I
DxA
= I
DxC
= 30mA Max.). Under maximum output current conditions, special attention must be given to input voltage and
LED forward voltage to ensure proper current regulation. See the Maximum Output Current section of the datasheet for more
information.
(5) For the Main Display group of outputs on a part, the following are determined: the maximum output current in the group (MAX), the
minimum output current in the group (MIN), and the average output current of the group (AVG). Two matching numbers are calculated:
(MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure for the bank. The
typical specification provided is the most likely norm of the matching figure for all parts.
(6) For each I
Dxx
output pin, headroom voltage is the voltage across the internal current sink connected to that pin. For Main and Aux
outputs, V
HR
= V
OUT
-V
LED
. If headroom voltage requirement is not met, LED current regulation will be compromised.
(7) SCL and SDIO signals are referenced to VIO and GND for minimum VIO voltage testing.
(8) SCL and SDIO should be glitch-free in order for proper brightness control to be realized.
4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM27966
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