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Understanding and Performing MIPI
®
D-PHY Physical Layer, CSI and DSI Protocol Layer Testing
Electrical Signal Challenges
A D-PHY interface can have a minimum configuration of one
clock lane and one data lane, and a maximum configuration
of one clock lane and four data lanes. As shown in Figure 2,
each data lane operates in one of two modes: High Speed
or Low Power. This means that the same two physical data
paths alternate between high speed differential signaling and
low power single-ended signaling.
In High Speed (HS) mode, the differential voltage is 140 mV
min, 200 mV nominal, 270 mV max, with the data rate
extending up to 1 Gb/s. The HS mode consists of two
possible states: Differential-0 (HS-0) and Differential-1 (HS-1).
In Low Power (LP) mode, the signaling is two single-ended
with 1.2 V swing operating at a maximum data rate of 10 Mb/s.
The LP mode consists of four possible states: LP-00, LP-01,
LP-10, and LP-11. In addition, the rise times in the HS mode
are different from that of the LP mode.
Figure 2. Modes and States in a D-PHY Data lane.
Figure 3. Modes and States in a D-PHY Clock lane.