IEEE 1588 Version 2: 2008网络测量与控制系统精密时钟同步协议

1588

需积分: 9 42 浏览量更新于2024-07-18 收藏 3.45MB PDF 举报

身份认证购VIP最低享 7 折!

30元优惠券

IEEE 1588 Version 2, 2008（修订版 IEEE 1588-2002）是IEEE针对网络测量与控制系统设计的一个精确时钟同步协议标准。这个标准由IEEE Instrumentation and Measurement Society的Sensor Technology Technical Committee (TC-9) 主导，并于2008年3月27日获得批准，由IEEE标准化委员会（IEEE-SA Standards Board）授权。该标准的目的是为了提高网络中时间同步的精度和可靠性，这对于工业自动化、电力系统控制、通信基础设施等领域的实时应用至关重要。该协议的核心目标是实现亚微秒级的时间同步，以确保网络中各节点的时间戳高度一致，从而支持高精度的时间同步应用，如电力系统保护、远程监控和自动化测试。IEEE 1588 Version 2相较于前一代（IEEE 1588-2002）进行了多项改进，包括增强的透明度、可靠性和鲁棒性，以及对不同网络拓扑的支持，例如星形、环形和混合网络结构。协议采用分层结构，分为三个主要部分：Announce、Follow-up和Sync，每个阶段都包含了一系列详细的操作步骤和机制。Announce阶段用于初始化时钟同步，节点通过发送Announce报文来宣告自己的时钟状态；Follow-up阶段则是通过交互消息来进一步调整时钟，确保时钟精度；而Sync阶段则是周期性的同步过程，以保持整个网络的长期稳定同步。 IEEE 1588 Version 2引入了新的功能，如BMC（Best Master Clock）算法，用于选举网络中的最优时钟源，以及BMC备份机制，以防主时钟失效。此外，该版本还定义了时间戳精度等级，允许不同的应用根据其需求选择合适的同步级别。在实际部署中，IEEE 1588 Version 2可能涉及硬件和软件的升级，以支持新的同步机制和协议特性。同时，它还需要网络设备供应商和用户共同遵循标准规范，确保设备之间的兼容性和互操作性。总结来说，IEEE 1588 Version 2 2008标准是一个关键的技术里程碑，它提升了网络时间同步的性能，对于那些依赖于高精度时间同步的工业自动化和控制系统的稳定运行具有重要意义。任何想要实现或优化此类系统的设计者和工程师都需要深入理解和掌握这一标准。

资源详情

资源推荐

xiv

Table 105 ⎯Translation of flagField from version 2 to version 1 ...................................................... 181

Table 106 ⎯Version 2 fields with no version 1 counterpart............................................................... 182

Table 107 ⎯Version 1 fields with no version 2 counterpart............................................................... 183

Table 108 ⎯Name correspondence..................................................................................................... 183

Table 109 ⎯Mixed system restrictions............................................................................................... 184

Table B.1⎯Relationships between timescales........................................................................................... 199

Table C.1⎯Interpretation of Figure C.1 key values .................................................................................. 202

Table C.2⎯Interpretation of Figure C.2 key values .................................................................................. 203

Table C.3⎯Interpretation of Figure C.3 key values .................................................................................. 205

Table C.4⎯Interpretation of Figure C.4 key values .................................................................................. 207

Table C.5⎯Interpretation of Figure C.5 key values .................................................................................. 209

Table C.6—Interpretation of Figure C.6 key values .................................................................................. 210

Table C.7—Interpretation of Figure C.7 key values .................................................................................. 211

Table C.8—Interpretation of Figure C.8 key values .................................................................................. 213

Table C.9—Interpretation of Figure C.9 key values .................................................................................. 215

Table C.10—Interpretation of Figure C.10 key values............................................................................... 217

Table C.11—Interpretation of Figure C.11 key values............................................................................... 218

Table D.1⎯IPv4 multicast addresses......................................................................................................... 219

Table D.2⎯transportSpecific field values ................................................................................................. 220

Table E.1⎯IPv6 multicast addresses ......................................................................................................... 222

Table F.1⎯Multicast MAC addresses ....................................................................................................... 223

Table F.2⎯Ethernet transport specific field............................................................................................... 224

Table G.1⎯DeviceNet clockIdentity octets 0 through 7............................................................................ 226

Table G.2⎯DeviceNet headers for all PTP message packets .................................................................... 226

Table H.1⎯ControlNet clockIdentity octets 2 through 7........................................................................... 228

Table I.1⎯Mapping of messages............................................................................................................... 231

Table I.2⎯IEEE 802.3 DLPDU syntax ..................................................................................................... 232

Table I.3⎯Multicast MAC address............................................................................................................ 233

Table I.4⎯LT (Length/Type)..................................................................................................................... 234

Table I.6⎯Mapping of the parameter and attribute names ........................................................................ 235

Table I.7⎯Translation of flagField from PTP version 2 to PROFINET.................................................... 236

Table K.1⎯flagField.SECURE flag .......................................................................................................... 242

Table K.2⎯AUTHENTICATION TLV .................................................................................................... 260

Table K.3⎯algorithmId values .................................................................................................................. 261

Table K.4⎯ICV and pad length................................................................................................................. 261

Table K.5⎯AUTHENTICATION_CHALLENGE TLV .......................................................................... 262

Authorized licensed use limited to: New Jersey Institute of Technology. Downloaded on December 23, 2008 at 17:05 from IEEE Xplore. Restrictions apply.

xvi

FIGURES

Figure 1 ⎯Mealy state transition diagram .............................................................................................. 10

Figure 2 ⎯Model of an ordinary clock ................................................................................................... 19

Figure 3 ⎯Model of a boundary clock.................................................................................................... 21

Figure 4 ⎯Model of an end-to-end transparent clock ............................................................................. 22

Figure 5 ⎯End-to-end residence time correction model......................................................................... 23

Figure 6 ⎯Combined ordinary and end-to-end transparent clock........................................................... 25

Figure 7 ⎯Model of a peer-to-peer transparent clock............................................................................. 27

Figure 8 ⎯Peer-to-peer residence time and link delay correction model................................................ 28

Figure 9 ⎯Combined ordinary and peer-to-peer transparent clock. ....................................................... 30

Figure 10 ⎯Simple master−slave clock hierarchy ............................................................................... 32

Figure 11 ⎯Pruned mesh topology ...................................................................................................... 33

Figure 12 ⎯Basic synchronization message exchange ........................................................................ 34

Figure 13 ⎯Link delay measurement................................................................................................... 35

Figure 14 ⎯Timestamp generation model............................................................................................ 36

Figure 15 ⎯Hierarchical topology ....................................................................................................... 37

Figure 16 ⎯Linear topology................................................................................................................. 38

Figure 17 ⎯Multiply connected topology............................................................................................ 39

Figure 18 ⎯Bridging disparate technologies........................................................................................ 40

Figure 19 ⎯Definition of latency constants ......................................................................................... 45

Figure 20 ⎯Propagation asymmetry .................................................................................................... 47

Figure 21 ⎯Port model ........................................................................................................................ 48

Figure 22 ⎯Scaled log variance hysteresis .......................................................................................... 60

Figure 23 ⎯State machine for a full implementation........................................................................... 78

Figure 24 ⎯State machine for a slave-only implementation................................................................ 79

Figure 25 ⎯STATE_DECISION_EVENT logic ................................................................................. 81

Figure 26 ⎯State decision algorithm ................................................................................................... 87

Figure 27 ⎯Data set comparison algorithm, part 1 .............................................................................. 89

Figure 28 ⎯Data set comparison algorithm, part 2 .............................................................................. 90

Figure 29 ⎯Receipt of Announce message logic................................................................................. 96

Figure 30 ⎯Receipt of Sync message logic ......................................................................................... 98

Figure 31 ⎯Receipt of Follow_Up message logic ............................................................................. 100

Figure 32 ⎯Receipt of Delay_Req message logic ............................................................................. 101

Figure 33 ⎯Receipt of Delay_Resp message logic............................................................................ 103

Figure 34 ⎯Delay request-response path length measurement.......................................................... 110

Authorized licensed use limited to: New Jersey Institute of Technology. Downloaded on December 23, 2008 at 17:05 from IEEE Xplore. Restrictions apply.

xvii

Figure 35 ⎯Peer delay link measurement .......................................................................................... 113

Figure 36 ⎯Permitted mixed system configuration ........................................................................... 183

Figure 37 ⎯Profile print form............................................................................................................ 186

Figure C.1⎯Master, end-to-end, and slave one-step clocks; no asymmetry correction ............................ 201

Figure C.2⎯Master, end-to-end, and slave one-step clocks; with asymmetry correction ......................... 202

Figure C.3⎯Master two-step and end-to-end transparent and slave one-step clocks; with asymmetry

correction.................................................................................................................................................... 204

Figure C.4⎯Master and end-to-end transparent, two-step, and one-step, slave clocks; with asymmetry

correction.................................................................................................................................................... 206

Figure C.5⎯One-step master, two-step end-to-end transparent, and one-step slave clocks; with asymmetry

correction.................................................................................................................................................... 208

Figure C.6—One-step peer responder, end-to-end transparent, and peer requestor clocks; with asymmetry

correction.................................................................................................................................................... 210

Figure C.7—One-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks;

with asymmetry correction ......................................................................................................................... 211

Figure C.8—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 1; with asymmetry correction.......................................................................................................... 212

Figure C.9—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 2; with asymmetry correction.......................................................................................................... 214

Figure C.10—Two-step peer responder, one-step end-to-end transparent, and one-step peer requestor

clocks: option 2; with asymmetry correction.............................................................................................. 216

Figure C.11—One-step peer master, two-step peer-to-peer transparent, and one-step peer slave clocks; time

computation................................................................................................................................................ 217

Figure G.1⎯ Event message timestamp point ........................................................................................... 225

Figure I.1⎯PROFINET region combined with domains........................................................................... 231

Figure K.1⎯PTP secure message processing ............................................................................................ 252

Figure K.2⎯Challenge processing............................................................................................................. 254

Figure K.3⎯Secure transmit processing.................................................................................................... 256

Figure K.4⎯Secure event processing ........................................................................................................ 258

Authorized licensed use limited to: New Jersey Institute of Technology. Downloaded on December 23, 2008 at 17:05 from IEEE Xplore. Restrictions apply.